Abstract: A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected.

Abstract: A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected.

Abstract: The HBT-based transient suppression device contains a collector layer of a first conduction type, a base layer of a second conduction type, an emitter layer of the first conduction type, stacked in this order sequentially on a top side of a heavily doped substrate of the first conduction type. The doping concentration of the base layer is higher than that of the emitter and collector layers, and that the thickness of the collector layer is less than 300 nm, so that the BVCEO breakdown voltage is reduced below 5V Additionally, the thickness of the base layer is larger than the sum of the thickness of a section of the emitter-base depletion region extending into the base layer and the thickness of a section of the base-collector depletion region extending into the base layer, so that the base layer is not operated in a punch-through condition.

Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.

Abstract: A negative voltage detector includes a first n-channel transistor having a coupled gate node and drain node, a second n-channel transistor having a gate coupled to the gate of the first n-channel transistor, a first current source coupled to a drain of the first n-channel transistor, a second current source coupled to a drain of the second n-channel transistor, an output terminal coupled to the drain of the second n-channel transistor, and an input terminal coupled to a source of the first n-channel transistor. The gate voltage of the first n-channel transistor, i.e., the gate voltage of the second n-channel transistor, depends on its source voltage (the voltage of the input terminal), and the switching operation of the second n-channel transistor can be performed by controlling the voltage of the input terminal to change the output voltage of the output terminal.

Abstract: A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1-x, 0.0?x?1.0) and/or indium-gallium-arsenic-nitride (InyGa1-yAszN1-z, 0.0?y, z?1.0) in a specific order is used to form the transistor base of a heterojunction bipolar transistor. By controlling the compositions of the materials indium-gallium-arsenic-nitride and gallium-arsenide-antimonide, and by changing the thickness and order of the layers, the new material would possess a specific energy gap, which in turn determines the base-emitter turn-on voltage of the heterojunction bipolar transistor.

Abstract: The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.

Abstract: A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1?x, 0.0?x?1.0) and/or indium-gallium-arsenic-nitride (InyGa1?yAszN1?z, 0.0?y, z?1.0) in a specific order is used to form the transistor base of a heterojunction bipolar transistor. By controlling the compositions of the materials indium-gallium-arsenic-nitride and gallium-arsenide-antimonide, and by changing the thickness and order of the layers, the new material would possess a specific energy gap, which in turn determines the base-emitter turn-on voltage of the heterojunction bipolar transistor.