Patents by Inventor Chao-Hsun Lin

Chao-Hsun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240384554
    Abstract: The present application provides a structural strengthening device to improve the lateral strength of a building frame. This most basic form of this device consists of one structural (connecting) member, two beam-column connectors, and the buffering material. By connecting adjacent columns in the frame, resisting moments will be generated at the ends of the connecting member(s) during lateral deformation of the frame, and the bending moments and stresses at the base of the connected columns can be reduced. Implementation of this device does not only reduce the time and space required for structural rehabilitation of buildings, the “detachable” feature of this device also allows the owner to use this device as a temporary (reusable) or permanent rehabilitation measure.
    Type: Application
    Filed: May 10, 2024
    Publication date: November 21, 2024
    Inventors: Chao-Hsun Huang, Ea-Shin Lin, Po-Cheng Lian, Zhen-Jun Zheng
  • Publication number: 20240387660
    Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Chia-Hsien Yao, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240379432
    Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 14, 2024
    Inventors: Shih-Che Lin, Chao-Hsun Wang, Chia-Hsien Yao, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12142565
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Publication number: 20240355730
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Patent number: 12074063
    Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Che Lin, Chao-Hsun Wang, Chia-Hsien Yao, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240277865
    Abstract: Disclosed herein is a phage-displayed single-chain variable fragment (scFv) library, which comprises a plurality of phage-displayed scFvs characterized with a specific sequence in each CDR. The present phage-displayed scFv library is useful in selecting an antibody fragment exhibiting a binding affinity and specificity to mesothelin (MSLN). Also disclosed herein are a recombinant antibody specific to MSLN, an immunoconjugate comprising the recombinant antibody, and uses thereof in treating cancers.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 22, 2024
    Inventors: An-Suei YANG, Hung-Ju HSU, Chao-Ping TUNG, Chung-Ming YU, Chi-Yung CHEN, Hong-Sen CHEN, Yu-Chuan HUANG, Pei-Hsun TSAI, Szu-Yu LIN, Hung-Pin PENG
  • Patent number: 12057392
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Patent number: 10492319
    Abstract: A method of making a housing includes: providing a substrate and cutting the substrate to form an opening. The substrate being spaced by the opening to form at least one main base. A plurality of metal sheets and a plurality of reinforcing members are provided. Placing the metal sheets, the reinforcing members and the main base into a mold. The metal sheets is positioned in the opening, adjusts width of each gap between adjacent metal sheets, and between the main base and one metal sheet adjacent to the main base. Locating the reinforcing members in the metal sheets and the main base. Liquid resin is filled into the gaps and covers the reinforcing members to bond the metal sheets, the main base and the reinforcing members together, forming the housing.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 26, 2019
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: Chang-Hai Gu, Wu-Zheng Ou, Chao-Hsun Lin, Xiao-Kai Liu
  • Patent number: 10353440
    Abstract: A housing includes a metal base and a non-conductive member. The metal base has an internal surface and a plurality of gap. The non-conductive member covers at least a portion of the internal surface of the metal base, and the non-conductive member is formed on the bottom of the at least one gap. The metal base is spaced by the gaps to form a plurality of metal sheets and at least one main body. Each gap is completely filled with one dielectric member. The metal sheets and the at least one main body are all bonded with the dielectric member and are electrically isolated with each other.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 16, 2019
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: Wu-Zheng Ou, Chang-Hai Gu, Chao-Hsun Lin, Xiao-Kai Liu, Wei-Ben Chen
  • Patent number: 10230158
    Abstract: A method of making a housing includes providing a substrate having an opening, providing a plurality of metal sheets, providing a plurality of non-conductive members, and bonding the metal sheets together through the non-conductive members, forming a metal sheets member, placing the metal sheets member in the opening, bonding the metal sheets member with the substrate through the non-conductive members, and removing excess parts of the substrate to form the housing.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: March 12, 2019
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: Wei-Ben Chen, Min Liu, Chao-Hsun Lin, Chao Lan
  • Publication number: 20170324152
    Abstract: A method of making a housing includes providing a substrate having an opening, providing a plurality of metal sheets, providing a plurality of non-conductive members, and bonding the metal sheets together through the non-conductive members, forming a metal sheets member, placing the metal sheets member in the opening, bonding the metal sheets member with the substrate through the non-conductive members, and removing excess parts of the substrate to form the housing.
    Type: Application
    Filed: July 25, 2017
    Publication date: November 9, 2017
    Inventors: WEI-BEN CHEN, MIN LIU, CHAO-HSUN LIN, CHAO LAN
  • Patent number: 9755297
    Abstract: A housing includes a substrate having an opening, a plurality of metal sheets and a plurality of non-conductive members, the metal sheets are bonded with each other through non-conductive members, forming a metal sheets member, the metal sheets member is located in the opening, the metal sheets member is bonded with substrate through the non-conductive members.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: September 5, 2017
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: Wei-Ben Chen, Min Liu, Chao-Hsun Lin, Chao Lan
  • Patent number: 9728839
    Abstract: A housing includes a substrate having an opening, a plurality of metal sheets and a plurality of reinforcing members, the metal sheets are positioned in the opening, the reinforcing members inlaid in the metal sheets and the substrate. The present invention also provides an electronic device having the housing, and a method of making the housing.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: August 8, 2017
    Assignees: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: Chang-Hai Gu, Wu-Zheng Ou, Chao-Hsun Lin, Xiao-Kai Liu
  • Publication number: 20170220079
    Abstract: A method of making a housing includes: providing a metal base, the metal base having an internal surface. Placing the metal base into a mold, liquid non-conductive material covering at least a portion of the internal surface of the metal base to form a non-conductive member at the at least a portion of the metal base. Cutting the metal base corresponding to the at least a portion of the metal base to form at least one gap, the non-conductive member being formed on a bottom of the gap. Placing one dielectric member in one corresponding gap.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: WU-ZHENG OU, CHANG-HAI GU, CHAO-HSUN LIN, XIAO-KAI LIU, WEI-BEN CHEN
  • Publication number: 20170223852
    Abstract: A method of making a housing includes: providing a substrate and cutting the substrate to form an opening. The substrate being spaced by the opening to form at least one main base. A plurality of metal sheets and a plurality of reinforcing members are provided. Placing the metal sheets, the reinforcing members and the main base into a mold. The metal sheets is positioned in the opening, adjusts width of each gap between adjacent metal sheets, and between the main base and one metal sheet adjacent to the main base. Locating the reinforcing members in the metal sheets and the main base. Liquid resin is filled into the gaps and covers the reinforcing members to bond the metal sheets, the main base and the reinforcing members together, forming the housing.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: CHANG-HAI GU, WU-ZHENG OU, CHAO-HSUN LIN, XIAO-KAI LIU
  • Publication number: 20170212553
    Abstract: A housing includes a metal base and a non-conductive member. The metal base has an internal surface and a plurality of gap. The non-conductive member covers at least a portion of the internal surface of the metal base, and the non-conductive member is formed on the bottom of the at least one gap. The metal base is spaced by the gaps to form a plurality of metal sheets and at least one main body. Each gap is completely filled with one dielectric member. The metal sheets and the at least one main body are all bonded with the dielectric member and are electrically isolated with each other.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Inventors: WU-ZHENG OU, CHANG-HAI GU, CHAO-HSUN LIN, XIAO-KAI LIU, WEI-BEN CHEN
  • Publication number: 20160352007
    Abstract: A housing includes a metallic base defining a slit, a plurality of metallic members arranged in the slit at intervals, and a non-conductive member formed between each two neighboring metallic members and between the metallic base and the metallic members adjacent to the metallic base. The plurality of the metallic pieces and the metallic base are connected by the non-conductive member. An electronic device including the housing and a method of manufacturing the housing are also provided.
    Type: Application
    Filed: March 23, 2016
    Publication date: December 1, 2016
    Inventors: CHANG-HAI GU, WU-ZHENG OU, CHAO-HSUN LIN, XIAO-KAI LIU
  • Publication number: 20160187932
    Abstract: A housing includes a substrate defining a surface, and at least one seal ring formed on the substrate, the seal ring is made of elastic material, a surface of the seal ring connected with the substrate has a plurality of ribs, the surface of the substrate connecting with the seal ring has a plurality of holes, the ribs are engaged in the holes. A method of making a housing includes: a substrate defining a surface is provided; a plurality of holes is formed on the substrate; and at least one seal ring is formed on the substrate, the seal ring has a plurality of ribs, the ribs are engaged in the holes.
    Type: Application
    Filed: January 27, 2015
    Publication date: June 30, 2016
    Inventors: CHAO-HSUN LIN, YI-TING YEH, LI-HONG NA, YUAN-XIONG LIU
  • Publication number: 20160184969
    Abstract: An abrasive article includes a non-rigid carrier and a plurality of abrasive particles disposed in the carrier, the carrier is made of resin or rubber, a mass ratio of abrasive particles to carrier is about 1:1 to about 5:1. A method for making the abrasive articles includes providing a plurality of abrasive particles and a resin, mixing the rubber and the abrasive particles, heating the mixture to a fluid state, and pressing the mixture into a desired shape. After the mixed is cooled, the mixture is cut into small pellets, forming the abrasive articles.
    Type: Application
    Filed: January 28, 2015
    Publication date: June 30, 2016
    Inventors: XIAO-KAI LIU, CHANG-HAI GU, CHAO-HSUN LIN, WEI-BEN CHEN, BO LI