Patents by Inventor Chao Hua

Chao Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153881
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Publication number: 20240136280
    Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Publication number: 20240111473
    Abstract: A distributed display method provides different parts of an application interface that are collaboratively displayed on a plurality of terminals, so that manners for collaborative display between the plurality of terminals are more flexible and richer. A first terminal displays a first interface including a first part and a second part. When the first terminal detects that a preset condition is met, the first terminal displays a second interface, where the second interface includes the first part and does not include the second part; and the first terminal notifies a second terminal to display a third interface, where the third interface includes the second part and does not include the first part.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 4, 2024
    Inventors: Zhen Wang, Bo Qiang, Bingxin Sun, Yanan Zhang, Hongjun Wang, Junjie Si, Mengzheng Hua, Gang Li, Cheng Luo, Xiaoxiao Duan, Wei Li, Chao Xu
  • Publication number: 20240107682
    Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.
    Type: Application
    Filed: April 21, 2023
    Publication date: March 28, 2024
    Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240096740
    Abstract: Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Chiu, Chao-Wei Li, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240088804
    Abstract: Provided is a motor braking device for a N-phase brushless motor. The motor braking device includes a switching circuit adapted to connect the N-phase brushless motor to a power supply, the switching circuit comprising a high side switch group and a low side switch group, each of the high side switch group and the low side switch group comprising N switching elements, and a control unit configured to control the switching circuit to brake the motor based on occurrence of a first event, the first event chosen from a group consisting of release of a trigger by a user, and occurrence of a predetermined condition as detected by a sensor. The control unit is configured to, upon occurrence of the first event, switch all the switching elements of one of the high side switch group or the low side switch group to an on-state, and simultaneously switch all the switching elements of the other one of the high side switch group and the lower side switch group to an off-state.
    Type: Application
    Filed: February 10, 2021
    Publication date: March 14, 2024
    Inventors: Bao An ZHANG, Zi Cong CHEN, Li Hua XIE, Chao WEN, Yong Min LI
  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Publication number: 20240079758
    Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Wen-Hgin Chuang, Lin-Hsu Chiang, Chang-Hua Wu, Han-Wei Wang, Chun-Jung Hu
  • Patent number: 11917955
    Abstract: Apparatus, systems and methods for irrigating lands are disclosed. In one example, an irrigation system is disclosed. The irrigation system includes a gate and a microcontroller unit (MCU). The gate is configured for adjusting a water flow for irrigating a piece of land. The MCU is configured for controlling the gate to adjust the water flow based on environmental information related to the piece of land.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Cheng Huang, Tai-Hua Yu, Shui-Ting Yang, Chao-Te Lee, Ching Rong Lu
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Publication number: 20240071952
    Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.
    Type: Application
    Filed: January 10, 2023
    Publication date: February 29, 2024
    Inventors: Chih-Chiang Tsao, Hsuan-Ting Kuo, Chao-Wei Chiu, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20230334833
    Abstract: An image processing method is performed by a computer device, which includes: converting initial image data into super-resolution image data using a trained image processing network, a resolution of the super-resolution image data being greater than or equal to a target resolution; performing image quality enhancement processing on the super-resolution image data using the trained image processing network, to obtain first enhanced image data; when there is a face image in the first enhanced image data, performing face enhancement on the face image in the first enhanced image data using the trained image processing network to obtain second enhanced image data; and performing image sharpening processing on the second enhanced image data using the trained image processing network to obtain sharpened image data.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 19, 2023
    Inventors: Shichang SHI, Fei Huang, Chao Hua, Wei Xiong, Liang Yang
  • Publication number: 20230219820
    Abstract: A cracking process for a reaction distillation of chlorosilane slurry includes feeding a chlorosilane slurry into a phase separator, drying a solid phase, feeding a chlorosilane polymer into a plate distillation column, returning kettle materials of the plate distillation column, and dividing a material produced from a top of the column. The process adopts an ionic liquid catalyst, which is environmentally friendly and reusable. The cracking and distillation of chlorosilane polymer are carried out simultaneously to shorten the time and increase the utilization rate of raw materials, which can reduce energy consumption and save costs and facilitate industrial production. A plate column is used as a distillation column, in which the two phases of the gas and liquid are sufficiently contacted. Therefore, the transfer of mass and heat is good, the production capacity is good, and the tower is not easily blocked, thereby making it easy to clean.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 13, 2023
    Applicant: Institute of Process Engineering, Chinese Academy of Sciences
    Inventors: Chao HUA, Hongxing WANG, Fang BAI, Ping LU, Hai LI
  • Publication number: 20230198098
    Abstract: Disclosed are a separator membrane, a separator membrane roll, a battery cell, and a power lithium battery. The separator membrane includes a porous base film and a bonding layer; in a preset direction of the porous base film, the surface of the porous substrate includes a middle blank area, and a coated area at the two ends; the bonding layer is applied on the two coated areas. By means of applying the bonding layer to both ends of the porous base film surface, it is possible, during the process of assembling and forming the lithium battery cell, to cause the bonding layer to contact and bond with the two ends of the negative electrode inside the lithium battery cell, effectively ensuring that the lithium battery bears sufficient tension, pressure, and vibration during assembly, vibration testing, and long-term cycling.
    Type: Application
    Filed: July 27, 2021
    Publication date: June 22, 2023
    Applicants: JIANGSU SENIOR NEW MATERIAL TECHNOLOGY CO., LTD, SHENZHEN SENIOR TECHNOLOGY MATERIAL CO., LTD.
    Inventors: Xiang PING, Chao HUA, Baocheng ZHONG, Xiaobao YE, Xuemei YANG, Xiufeng CHEN
  • Patent number: 11551169
    Abstract: An industrial device matching method and apparatus are used for acquiring a corresponding relationship between industrial devices in different industrial data sources to provide basis for industrial data analysis. The method, in an embodiment, includes collecting data of at least two industrial data sources; determining a first relationship between various industrial devices in each industrial data source, and determining a first relationship topology between the industrial devices in the industrial data source; and comparing the first relationship topologies corresponding to various industrial data sources, to determine a first corresponding relationship between industrial devices in industrial data sources, the first corresponding relationship enabling the first relationship topologies corresponding to at least two industrial data sources to be similar.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: January 10, 2023
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Chao Hua Wu, Cong Chao Li, Daniel Schneegass, Ruo Gu Sheng, Peng Wei Tian
  • Patent number: 11308649
    Abstract: A device implementing the subject pixel storage for graphical frame buffers may include at least one processor configured to obtain a plurality of data units containing a plurality of pixels stored in memory, each of the plurality of data units including a first pixel of the plurality of pixels packed in succession with at least a portion of a second pixel of the plurality of pixels, in which the plurality of pixels is represented by a number of bits, obtain a group of pixels from the plurality of pixels, and store the group of pixels using a targeted number of bits. A method and computer program product implementing the subject pixel storage for graphical frame buffers is also provided.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 19, 2022
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Richard Hayden Wyman, Brian Francis Schoner, David Chao Hua Wu, Timothy James Mamtora
  • Patent number: 11199956
    Abstract: The system, method, and computer program product described herein provide unified real-time rule analytics to users through the use of an analytics logic editor that allows a user to construct an analytic logic rule unit that may be used on both edge and cloud devices. The user may select a data source, transform, rule condition, and action using an interface of the analytics logic editor to construct an analytics logic rule unit that may be deployed to both edge and cloud devices in real-time without the need to separately program each device. The analytics logic rule unit may be installed and executed by the edge and cloud device in real-time.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yao Liang Chen, Sheng Huang, Yun Jie Qiu, Xinlin Wang, Xiao Min Xu, Chao Hua Zhang
  • Patent number: D959633
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 2, 2022
    Assignee: I-DRINK PRODUCTS INC.
    Inventors: Chao-Hua Ye, Douglas Wang