Abstract: A charging method includes the following operations: charging an auxiliary power source and at least one charging power source simultaneously, in which a power demand of the auxiliary power source is a first consideration, and a power demand of the at least one charging power source is a second consideration; detecting an auxiliary current value of the auxiliary power source and a total charging current value of the at least one charging power source; and stopping charging the auxiliary power source when a sum of the auxiliary current value and the total charging current value is greater than a current threshold value.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A short-circuit current protecting method of a charging control system is cooperating with at least a control unit and a plurality of power outlet electrically connected to an electronic switch. The control unit controls the mode of the electronic switches with turn on or off. The short-circuit current protecting method includes the following steps. Step 1 is detecting at least a current signal value of an AC power. Step 2 is determining whether the current signal value is grater than a predetermine current threshold. Step 3 is enabling a short-circuit current analyzing module if the current signal value is grater than the predetermine current threshold. Step 4 is turning off at least one of the electronic switches if the short-circuit current is determined by the short-circuit current analyzing module.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A power charging management method is cooperated with a charging control system. The charging control system includes a control unit and a plurality of charging zones. The control unit controls the charging zones to turn on or turn off so as to selectively allow a charging power to be provided to the charging zones. The power charging management method includes a system scan procedure, a whole zone charging procedure, a protecting procedure and a subzone charging procedure.

Abstract: An intelligent charging system comprises a first switching element, a phase detecting device, a current detecting device and a controller. The first switching element is turned on or off based on a first control signal. The phase detecting device is configured to determine an allowable phase time interval of a phase of a power source. The current detecting device is connected to the first switching element. The current detecting device is configured to detect a first turned on time point when the first switching element is turned on. The controller is connected to the phase detecting device and the current detecting device. The controller is configured to determine whether the first turned on time point is within the allowable phase time interval. If the first turned on time point is not within the allowable phase time interval, the controller resets a first control parameter of the first control signal.

Abstract: A power charging management method is cooperated with a charging control system. The charging control system includes a control unit and a plurality of charging zones. The control unit controls the charging zones to turn on or turn off so as to selectively allow a charging power to be provided to the charging zones. The power charging management method includes a system scan procedure, a whole zone charging procedure, a protecting procedure and a subzone charging procedure.