Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Abstract: A charging system and a method of charging an electric window covering are disclosed. The electric window covering includes a power supply device and an electric power input, which is provided in a frame and coupled to the power supply device. The charging system includes a charging device, which includes an extension object, an electric power output, and a power storage device which stores a power. The electric power output and the power storage device are respectively connected to the extension object, which is erectable in a longitudinal direction thereof. When the charging device is connected to the frame and suspended therefrom, the power of the power storage device is transmitted to the electric power output through the extension object, and then provided to the electric power input, whereby to charge the power supply device. Therefore, the method can be easily performed with said charging system.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.

Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: Methods and apparatus for removing particles from a substrate surface after a chemical mechanical polish. In some embodiments, the apparatus may include a manifold configured to receive and atomize a fluid and at least one spray nozzle mounted to the manifold and configured to spray the atomized fluid in a divergent spray pattern such that the substrate surface is cleansed when impinged by spray from the at least one spray nozzle, wherein the at least one spray nozzle sprays the atomized fluid at a pressure of approximately 30 psi to approximately 2500 psi.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A head-up display system includes a display device, a liquid crystal cell and a driver circuit. The display device is configured to generate multiple images at a frame rate. Each image includes multiple image segments with an initial polarization. The liquid crystal cell includes multiple addressable segments. The addressable segments are aligned with the image segments. The addressable segments are individually controllable to selectively adjust the initial polarization of the image segments between two different polarizations. The driver circuit is in communication with the display device and the liquid crystal cell. The driver circuit is configured to control the addressable segments to pass each image segment that has visible content to a user with the initial polarization switched between the two different polarizations at a frequency greater than the frame rate of the images and attenuate sunlight incident on the display device at each image segment that has blank content.

Abstract: A semiconductor package structure includes a conductive structure, a first semiconductor chip, a second semiconductor chip, a first encapsulant and an upper semiconductor chip. The first semiconductor chip is electrically connected to the conductive structure. The first semiconductor chip includes at least one first conductive element disposed adjacent to a second surface thereof. The second semiconductor chip is electrically connected to the conductive structure and disposed next to the first semiconductor chip. The second semiconductor chip includes at least one second conductive element disposed adjacent to a second surface thereof. The first encapsulant is disposed on the conductive structure to cover the first semiconductor chip and the second semiconductor chip. The first conductive element and the second conductive element are exposed from the first encapsulant.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

Abstract: An anechoic chamber includes a closed chamber and a metal container. The closed chamber includes wave-absorbing inner walls located therein, and the wave-absorbing inner walls collectively define a first accommodation space. Each of the wave-absorbing inner walls includes wave absorbers arranged thereon. The metal container is removably received in the first accommodation space, and has wave-reflecting inner walls located therein. The wave-reflecting inner walls collectively define a second accommodation space which is used to receive a device under test (DUT).

Abstract: The present disclosure provides a pressure sensor, including a chamber and a film. The chamber includes a first wall with a first electrode and a second wall with a second electrode. The first wall faces the second wall, and the first electrode and the second electrode respectively include conductive or semiconductive material. The film lines a surface inside the chamber exclusive of the first electrode and the second electrode for blocking outgassing entering the chamber from the surface. A method of manufacturing the pressure sensor is also disclosed.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A system and method for monitoring qualities of teaching and learning are provided. The system includes at least one receiving interface, a processor, and an output apparatus, wherein the processor is electrically connected to the at least one receiving interface and the output apparatus. The at least one receiving interface receives at least one digital image. The processor identifies at least one facial message from the at least one digital image, identifies at least one body message from the at least one digital image, and determines at least one teaching and learning quality index according to the at least one facial message and the at least one body message. The output apparatus outputs the at least one facial message, the at least one body message, and the at least one teaching and learning quality index.

Abstract: A light blocking system is disclosed, which is adapted to be used in a vertical blind which includes a headrail, a control mechanism provided in the headrail, and a covering assembly including a plurality of slats. Each of the slats is connected to the control mechanism with an end thereof, and therefore is hung below the headrail. A gap is left between the covering assembly and the headrail. The control mechanism is adapted to turn the slats in situ relative to the headrail, or to move the slats back and forth in a longitudinal direction of the headrail. The light blocking system includes a cover plate provided corresponding to the gap, wherein the cover plate covers the gap when the covering assembly is in a closed state.

Abstract: A semiconductor structure includes a memory array. The memory array has a plurality of memory units. The memory units include a first memory unit and a second memory unit. The first memory unit has a first resistance. The second memory unit has a second resistance. Both of the first resistance and the second resistance are in a range of 105? to 109?, and the second resistance is larger than the first resistance.