Abstract: A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.

Abstract: A leak inhibition/detection device includes an absorbent material, a leak sensor in contact with the absorbent material, and an enclosure surrounding the absorbent material. The leak inhibition/detection device is configured to surround a joint between tubing and a cold plate/evaporator or a radiator/condenser of a liquid cooling module of an information handling system.

Abstract: Pumping liners for use in an apparatus for depositing a material on a work piece by chemical vapor deposition includes a plurality of unevenly spaced apertures are disclosed. Uneven spacing of the plurality of apertures produces a uniform flow of processing gases within a processing chamber with which the pumping liner is associated. Films of materials deposited onto a work piece by chemical vapor deposition techniques using disclosed pumping liners exhibit desirable properties such as uniform thickness and smooth and uniform surfaces.

Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Abstract: An apparatus for packaging a semiconductor device is provided. The apparatus includes a first mold, a second mold and a support element. The first mold includes a plate. The second mold includes a carrier disposed corresponding to the plate. The carrier defines a hole penetrating the carrier. The support element is engaged with the hole for supporting an object to be molded.

Abstract: An apparatus for fabricating a semiconductor device has a housing defining a buffer chamber, a plurality of reactor ports formed in the housing for establishing interfaces with a plurality of process chambers that are to receive a wafer during a fabrication process to fabricate the semiconductor device, a wafer positioning robot positioned within the buffer chamber to transport the wafer between the plurality of process chambers through the plurality of reactor ports, a purge port formed in the housing for introducing a purge gas into the buffer chamber, a pump port formed in the housing for exhausting a portion of the purge gas from the buffer chamber, and a first flow enhancer that directs the purge gas flowing in an axial direction along a longitudinal axis of the purge port into the buffer chamber in a plurality of radial directions relative to the longitudinal axis.

Abstract: Methods and apparatus for chemical mechanical planarization (CMP) of a polymer or epoxy-based layer. In some embodiments, the method may comprise obtaining an endpoint for polymer or epoxy-based material for use in a CMP process, the CMP process configured to polish polymer or epoxy-based material, monitoring the polymer or epoxy-based layer with an endpoint detection apparatus configured to monitor polymer or epoxy-based material, polishing the polymer or epoxy-based layer with the CMP process, detecting when the polymer or epoxy-based layer has reached the endpoint for the CMP process, and halting the CMP process when the endpoint is detected. The endpoint detection apparatus may further comprise an optical detection apparatus configured to operate at a wavelength of approximately 200 nm to approximately 1700 nm to reduce step height of the polymer or epoxy-based layer.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A system for detecting an illuminance of the present invention includes a light source, a light sensor, and a signal output module. The light source includes a first A light-emitting diode, the first A light-emitting diode having a first color light; and the light source emits a first ray of light. The light sensor has a sensing face; the light sensor includes a first B light-emitting diode disposed on the sensing face, the first B light-emitting diode having the first color light; and the light sensor receives at least a portion of the first ray of light and generates a first sensing voltage. The signal output module is coupled to the light sensor to receive the first sensing voltage and output a sensing result signal according to the first sensing voltage.

Abstract: The present invention provides a composite intelligent biological phototherapy device including a base structure, a plurality of white light fluorescent tubes arranged side by side on the base structure, a plurality of LEDs disposed between the white light fluorescent tubes, a housing having an opening and configured to accommodate the base structure and the white light fluorescent tubes and the LEDs thereon, a light-transmittable plate disposed on the housing corresponding to the opening, and an control module configured to respectively control the white light fluorescent tubes and the LEDs. The base structure includes a plurality of sections, and each of the sections has a first surface facing the light-transmittable plate. The white light fluorescent tubes and the LEDs are provided on the first surfaces, and the sections are bent relative to each other so an angle between the first surfaces of adjacent sections is less than 180 degrees.

Abstract: An electric window covering is disclosed, which has a motorized assembly for controlling a movement of a covering material, a rechargeable battery for providing electric power to the motorized assembly, an electric power input at an overhead frame coupled with the rechargeable battery, and a separable charging device. The separable charging device has an electrical connector, a conductor and an electric power output provided at an extension object for charging the rechargeable battery through the electric power input. The separable charging device further has a first fixing structure at the extension object adapted to engage with a second fixing structure at the overhead frame for charging the rechargeable battery. After the extension object and the overhead frame are disengaged, the rechargeable battery still provides electric power to the motorized assembly for controlling the movement of the covering material.

Abstract: A charging method includes the following operations: charging an auxiliary power source and at least one charging power source simultaneously, in which a power demand of the auxiliary power source is a first consideration, and a power demand of the at least one charging power source is a second consideration; detecting an auxiliary current value of the auxiliary power source and a total charging current value of the at least one charging power source; and stopping charging the auxiliary power source when a sum of the auxiliary current value and the total charging current value is greater than a current threshold value.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A humidity-controlled storage device includes a plurality of panels configured to form an enclosed volume. A first panel of the plurality of panels includes inlet and outlet ports. The storage device further includes a purge system with a gas inlet pipe, a gas supply system, and a gas extraction system. The gas inlet pipe includes a nozzle and a cylindrical portion coupled to the inlet port. The gas supply system is configured to supply a purge gas to the gas inlet pipe. The gas inlet pipe is configured to output the purge gas into the enclosed volume in a direction that creates a circular or an oval gas flow pattern within the enclosed volume. The gas extraction system is coupled to the outlet port and is configured to extract the purge gas from the enclosed volume.

Abstract: A light guide plate has a light-incident surface, a bottom surface, a light-emitting surface, first microstructures and second microstructures. The bottom surface is opposite to the light-emitting surface, the light-incident surface is connected between the bottom surface and the light-emitting surface. The first microstructures protrude from the bottom surface and are arranged at intervals along a direction parallel to the light-incident surface and extend from the light-incident surface in a predetermined direction. The second microstructures are disposed between the first microstructures away from the light-incident surface, and each them includes light-adjusting blocks protruding from the bottom surface and arranged along the predetermined direction. Each first microstructure has a first height, and each light-adjusting block has a second height smaller than the first height. The light guide plate has a reduced horizontal viewing angle and a maintained luminance.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.