Patents by Inventor Chao-Kun Hu

Chao-Kun Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148303
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Patent number: 10192829
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Publication number: 20180005939
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Publication number: 20170358533
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Application
    Filed: August 7, 2017
    Publication date: December 14, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Patent number: 9759766
    Abstract: An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert E. Huang, Chao-Kun Hu, Baozhen Li, Paul S. McLaughlin
  • Patent number: 9754891
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Publication number: 20170176514
    Abstract: An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.
    Type: Application
    Filed: July 20, 2016
    Publication date: June 22, 2017
    Inventors: GRISELDA BONILLA, ELBERT E. HUANG, CHAO-KUN HU, BAOZHEN LI, PAUL S. MCLAUGHLIN
  • Publication number: 20170084540
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Patent number: 9472477
    Abstract: An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert E. Huang, Chao-Kun Hu, Baozhen Li, Paul S. McLaughlin
  • Patent number: 9111938
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 18, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC., Renesas Electronics Corporation, STMICROELECTRONICS, INC.
    Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
  • Patent number: 9059176
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 16, 2015
    Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC., Renesas Electronics Corporation, GLOBALFOUNDRIES, INC.
    Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
  • Publication number: 20150061135
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 5, 2015
    Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
  • Patent number: 8889546
    Abstract: A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Patent number: 8823176
    Abstract: An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Patent number: 8796853
    Abstract: An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Chao-Kun Hu
  • Publication number: 20130277842
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
  • Publication number: 20130221527
    Abstract: An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Chao-Kun Hu
  • Publication number: 20120329271
    Abstract: A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Publication number: 20120199976
    Abstract: An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.
    Type: Application
    Filed: April 17, 2012
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Chao-Kun Hu
  • Patent number: 8232646
    Abstract: An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Chao-Kun Hu, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang