Patents by Inventor Chao Min

Chao Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250062856
    Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.
    Type: Application
    Filed: June 6, 2024
    Publication date: February 20, 2025
    Inventors: Wanfen TENG, Yi-Min YU, Jason YEH, Chao-Lung WEI, Fan-Cheng HUANG, Yi-Wen SU, Ting-Chu YEH, Mei-Yi HUANG
  • Patent number: 12227865
    Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Min Lin, Hung-San Lu, Chao-Lung Chen, Chao Yuan Chang, Chun-An Kung, Chin-Hsin Hsiao, Wen-Chun Hou, Szu-Hung Yang, Ping-Ching Jiang
  • Publication number: 20250045222
    Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Applicant: Realtek Semiconductor Corp.
    Inventor: Chao-Min Lai
  • Patent number: 12218082
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20250038113
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Shuai-Lin LIU
  • Patent number: 12124307
    Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: October 22, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Chao-Min Lai, Chia-Chi Yeh, Chieh-Lung Hsieh, Chih-Feng Lin
  • Patent number: 12103142
    Abstract: A screwdriver tip structure includes a main body provided with an operation end. The operation end is provided with multiple first working sections and multiple second working sections. Each of the first working sections has a convex shape. Each of the second working sections has a concave shape. Each of the first working sections is provided with multiple grooves. Each of the first working sections has a first end and a second end. The second end has a diameter more than that of the first end. Each of the first working sections has a periphery provided with a phantom side face. The side face extends from the second end to the first end. Each of the grooves is provided with a first concave face. The first concave face of each of the grooves includes a first single arc.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 1, 2024
    Inventors: Chao-Min Hung, Bo-Wei Chen
  • Publication number: 20240316144
    Abstract: The present invention provides a method for inhibiting angiogenesis in a subject, which comprises administering said subject a pharmaceutical composition comprising beauvericin at a therapeutically effective concentration ranging from 0.1 ?M to 5 ?M. Also provides is the pharmaceutical composition comprising beauvericin at a therapeutically effective concentration ranging from 0.1 ?M to 5 ?M, and a pharmaceutically acceptable carrier.
    Type: Application
    Filed: February 6, 2024
    Publication date: September 26, 2024
    Applicant: ZIH YUAN TANG Biotechnology Co, Ltd.
    Inventors: Ming-Jai SU, Shoei-Sheng LEE, Feng-Chiao TSAI, Hou-Jen CHEN, Chao-Min HSU
  • Publication number: 20240322801
    Abstract: A multimedia device comprises a power input interface, a computing circuit and a load circuit. The power input interface is configured to receive an operating voltage. The computing circuit is configured to receive the operating voltage from the power input interface, and configured to output a pulse-width modulation (PWM) signal. The load circuit is configured to receive a test current from the power input interface, receive the PWM signal, and determine a magnitude of the test current according to a duty ratio of the PWM signal. The computing circuit is configured to monitor the variation of the operating voltage while adjusting the duty ratio of the PWM signal step by step. The computing circuit is configured to determine an upper bound of a power consumption of the computing circuit according to the relationship between the operating voltage and the duty ratio of the PWM signal.
    Type: Application
    Filed: March 22, 2024
    Publication date: September 26, 2024
    Inventors: Chao-Min LAI, Chien-Liang CHEN, Chia-Chi YEH
  • Patent number: 12046543
    Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: July 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Han-Chieh Hsieh, Chao-Min Lai, Cheng-Chen Huang, Nan-Chin Chuang
  • Patent number: 11983271
    Abstract: A processor may generate an enforcement point. The enforcement point may include one or more adversarial detection models. The processor may receive user input data. The processor may analyze, at the enforcement point, the user input data. The processor may determine, from the analyzing, whether there is an adversarial attack in the user input data. The processor may generate an alert based on the determining.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 14, 2024
    Assignee: International Business Machines Corporation
    Inventors: Bruno dos Santos Silva, Cheng-Ta Lee, Ron Williams, Bo-Yu Kuo, Chao-Min Chang, Sridhar Muppidi
  • Publication number: 20240045820
    Abstract: A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 8, 2024
    Inventors: CHAO-MIN LAI, YU-JEN LIN, HUNG-WEI WANG, HUANG-LIN KUO
  • Publication number: 20240009811
    Abstract: A screwdriver tip structure includes a main body provided with an operation end. The operation end is provided with multiple first working sections and multiple second working sections. Each of the first working sections has a convex shape. Each of the second working sections has a concave shape. Each of the first working sections is provided with multiple grooves. Each of the first working sections has a first end and a second end. The second end has a diameter more than that of the first end. Each of the first working sections has a periphery provided with a phantom side face. The side face extends from the second end to the first end. Each of the grooves is provided with a first concave face. The first concave face of each of the grooves includes a first single arc.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Inventors: Chao-Min Hung, Bo-Wei Chen
  • Patent number: 11854571
    Abstract: Apparatuses and methods of transmitting and receiving a speech signal. The method of transmitting a speech signal includes extracting low frequency feature information from an input speech signal by using a first feature extracting network; and transmitting a speech signal corresponding to the low frequency feature information to a receiving end. The method of receiving a speech signal includes receiving a first speech signal transmitted by a transmitting end; extracting low frequency feature information from the first speech signal and recovering high frequency feature information based on the low frequency feature information, by using a second feature extracting network; and outputting a second speech signal including the low frequency feature information and the high frequency feature information.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Liang Wen, Lizhong Wang, Anxi Yi, Chao Min, Liangxi Yao
  • Publication number: 20230376319
    Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.
    Type: Application
    Filed: January 3, 2023
    Publication date: November 23, 2023
    Inventors: Chao-Min LAI, Chien-Liang CHEN, Ming-Tsung TSAI
  • Patent number: 11768903
    Abstract: A computer-implemented method for automatically adjusting a Uniform Resource Locator (URL) seed list. The method includes crawling for documents based on a seed URL list. The method generates relations data from the documents using a Natural Language Processing (NLP) model. The method analyzes the relations data using an auto-seed model. The method modifies the seed URL list.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chao-Min Chang, Ying-Chen Yu, June-Ray Lin, Kuei-Ching Lee, Curtis C H Wei
  • Publication number: 20230299242
    Abstract: Discloded is a light emitting devices including an electroluminescent unit that emits the light of wavelength I, and a color conversion layer that absorbs the light of wavelength I and emits the light of wavelength II are disclosed. The color conversion layer comprises at least one color conversion material having a structural unit of formula (1) or (2). Display devices containing the light emitting devices are also disclosed.
    Type: Application
    Filed: April 14, 2023
    Publication date: September 21, 2023
    Applicant: Zhejiang Brilliant Optoelectronic Technology Co.,Ltd.
    Inventors: Chao MIN, Chacai LIANG, Caifa PAN
  • Patent number: 11764676
    Abstract: A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chao-Min Lai, Chien-Liang Chen, Hung-Wei Wang, Shih-An Yang
  • Publication number: 20230216904
    Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.
    Type: Application
    Filed: August 23, 2022
    Publication date: July 6, 2023
    Inventors: Chao-Min LAI, Chia-Chi YEH, Chieh-Lung HSIEH, Chih-Feng LIN
  • Patent number: 11663402
    Abstract: An approach for a fast and accurate word embedding model, “desc2vec,” for out-of-dictionary (OOD) words with a model learning from the dictionary descriptions of the word is disclosed. The approach includes determining that a target text element is not in a set of reference text elements, information describing the target text element is obtained. The information comprises a set of descriptive text elements. A set of vectorized representations for the set of descriptive text elements is determined. A target vectorized representation for the target text element is determined based on the set of vectorized representations using a machine learning model. The machine learning model is trained to represent a predetermined association between the set of vectorized representations for the set of descriptive text elements describing the target text element and the target vectorized representation.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chao-Min Chang, Kuei-Ching Lee, Ci-Hao Wu, Chia-Heng Lin