Patents by Inventor Chao Min
Chao Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250092491Abstract: Described herein is a chamber component having a body comprising one or more aluminum alloy compositions. A surface of the chamber component has an aluminum alloy composition comprising aluminum (Al), wherein the Al is included in an amount of about 85 wt % to about 98 wt %, based on total weight of the alloy composition, and magnesium (Mg), wherein the Mg is included in an amount of about 1 wt % to about 5 wt %, based on total weight of the alloy composition. The aluminum alloy composition further includes one or more additional chemical elements that form an equiaxed grain structure of an aluminum matrix of the alloy composition.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Inventors: Chien-Min Liao, Chao Liu, Tom Cho, Hyeon Geu Kim, Andrew Nguyen, Hari Ponnekanti, Mingdong Li, Changgong Wang, Bruce Alger
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Patent number: 12253895Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.Type: GrantFiled: January 3, 2023Date of Patent: March 18, 2025Assignee: Realtek Semiconductor CorporationInventors: Chao-Min Lai, Chien-Liang Chen, Ming-Tsung Tsai
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Publication number: 20250087601Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Po-Yuan SU
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Publication number: 20250079254Abstract: An electronic package is provided and includes: a thermally conductive chip; a circuit structure having a circuit layer; and an electronic component disposed between the circuit structure and the thermally conductive chip and electrically connected to the circuit layer, so as to dissipate the heat generated during the operation of the electronic component via the thermally conductive chip. A method of manufacturing the electronic package is further provided.Type: ApplicationFiled: January 4, 2024Publication date: March 6, 2025Inventors: Po-Yuan SU, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Che-Yu LEE
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Publication number: 20250062856Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.Type: ApplicationFiled: June 6, 2024Publication date: February 20, 2025Inventors: Wanfen TENG, Yi-Min YU, Jason YEH, Chao-Lung WEI, Fan-Cheng HUANG, Yi-Wen SU, Ting-Chu YEH, Mei-Yi HUANG
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Patent number: 12227865Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.Type: GrantFiled: July 25, 2022Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Che-Min Lin, Hung-San Lu, Chao-Lung Chen, Chao Yuan Chang, Chun-An Kung, Chin-Hsin Hsiao, Wen-Chun Hou, Szu-Hung Yang, Ping-Ching Jiang
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Publication number: 20250045222Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.Type: ApplicationFiled: July 31, 2024Publication date: February 6, 2025Applicant: Realtek Semiconductor Corp.Inventor: Chao-Min Lai
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Patent number: 12218082Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: GrantFiled: November 9, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20250038113Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.Type: ApplicationFiled: October 16, 2024Publication date: January 30, 2025Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Shuai-Lin LIU
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Patent number: 12124307Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.Type: GrantFiled: August 23, 2022Date of Patent: October 22, 2024Assignee: Realtek Semiconductor CorporationInventors: Chao-Min Lai, Chia-Chi Yeh, Chieh-Lung Hsieh, Chih-Feng Lin
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Patent number: 12103142Abstract: A screwdriver tip structure includes a main body provided with an operation end. The operation end is provided with multiple first working sections and multiple second working sections. Each of the first working sections has a convex shape. Each of the second working sections has a concave shape. Each of the first working sections is provided with multiple grooves. Each of the first working sections has a first end and a second end. The second end has a diameter more than that of the first end. Each of the first working sections has a periphery provided with a phantom side face. The side face extends from the second end to the first end. Each of the grooves is provided with a first concave face. The first concave face of each of the grooves includes a first single arc.Type: GrantFiled: July 7, 2022Date of Patent: October 1, 2024Inventors: Chao-Min Hung, Bo-Wei Chen
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Publication number: 20240316144Abstract: The present invention provides a method for inhibiting angiogenesis in a subject, which comprises administering said subject a pharmaceutical composition comprising beauvericin at a therapeutically effective concentration ranging from 0.1 ?M to 5 ?M. Also provides is the pharmaceutical composition comprising beauvericin at a therapeutically effective concentration ranging from 0.1 ?M to 5 ?M, and a pharmaceutically acceptable carrier.Type: ApplicationFiled: February 6, 2024Publication date: September 26, 2024Applicant: ZIH YUAN TANG Biotechnology Co, Ltd.Inventors: Ming-Jai SU, Shoei-Sheng LEE, Feng-Chiao TSAI, Hou-Jen CHEN, Chao-Min HSU
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Publication number: 20240322801Abstract: A multimedia device comprises a power input interface, a computing circuit and a load circuit. The power input interface is configured to receive an operating voltage. The computing circuit is configured to receive the operating voltage from the power input interface, and configured to output a pulse-width modulation (PWM) signal. The load circuit is configured to receive a test current from the power input interface, receive the PWM signal, and determine a magnitude of the test current according to a duty ratio of the PWM signal. The computing circuit is configured to monitor the variation of the operating voltage while adjusting the duty ratio of the PWM signal step by step. The computing circuit is configured to determine an upper bound of a power consumption of the computing circuit according to the relationship between the operating voltage and the duty ratio of the PWM signal.Type: ApplicationFiled: March 22, 2024Publication date: September 26, 2024Inventors: Chao-Min LAI, Chien-Liang CHEN, Chia-Chi YEH
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Patent number: 12046543Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.Type: GrantFiled: February 24, 2022Date of Patent: July 23, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Han-Chieh Hsieh, Chao-Min Lai, Cheng-Chen Huang, Nan-Chin Chuang
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Patent number: 11983271Abstract: A processor may generate an enforcement point. The enforcement point may include one or more adversarial detection models. The processor may receive user input data. The processor may analyze, at the enforcement point, the user input data. The processor may determine, from the analyzing, whether there is an adversarial attack in the user input data. The processor may generate an alert based on the determining.Type: GrantFiled: November 19, 2020Date of Patent: May 14, 2024Assignee: International Business Machines CorporationInventors: Bruno dos Santos Silva, Cheng-Ta Lee, Ron Williams, Bo-Yu Kuo, Chao-Min Chang, Sridhar Muppidi
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Publication number: 20240045820Abstract: A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.Type: ApplicationFiled: August 2, 2023Publication date: February 8, 2024Inventors: CHAO-MIN LAI, YU-JEN LIN, HUNG-WEI WANG, HUANG-LIN KUO
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Publication number: 20240009811Abstract: A screwdriver tip structure includes a main body provided with an operation end. The operation end is provided with multiple first working sections and multiple second working sections. Each of the first working sections has a convex shape. Each of the second working sections has a concave shape. Each of the first working sections is provided with multiple grooves. Each of the first working sections has a first end and a second end. The second end has a diameter more than that of the first end. Each of the first working sections has a periphery provided with a phantom side face. The side face extends from the second end to the first end. Each of the grooves is provided with a first concave face. The first concave face of each of the grooves includes a first single arc.Type: ApplicationFiled: July 7, 2022Publication date: January 11, 2024Inventors: Chao-Min Hung, Bo-Wei Chen
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Patent number: 11854571Abstract: Apparatuses and methods of transmitting and receiving a speech signal. The method of transmitting a speech signal includes extracting low frequency feature information from an input speech signal by using a first feature extracting network; and transmitting a speech signal corresponding to the low frequency feature information to a receiving end. The method of receiving a speech signal includes receiving a first speech signal transmitted by a transmitting end; extracting low frequency feature information from the first speech signal and recovering high frequency feature information based on the low frequency feature information, by using a second feature extracting network; and outputting a second speech signal including the low frequency feature information and the high frequency feature information.Type: GrantFiled: November 27, 2020Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Liang Wen, Lizhong Wang, Anxi Yi, Chao Min, Liangxi Yao
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Publication number: 20230376319Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.Type: ApplicationFiled: January 3, 2023Publication date: November 23, 2023Inventors: Chao-Min LAI, Chien-Liang CHEN, Ming-Tsung TSAI
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Patent number: 11768903Abstract: A computer-implemented method for automatically adjusting a Uniform Resource Locator (URL) seed list. The method includes crawling for documents based on a seed URL list. The method generates relations data from the documents using a Natural Language Processing (NLP) model. The method analyzes the relations data using an auto-seed model. The method modifies the seed URL list.Type: GrantFiled: June 19, 2020Date of Patent: September 26, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chao-Min Chang, Ying-Chen Yu, June-Ray Lin, Kuei-Ching Lee, Curtis C H Wei