Patents by Inventor Chao-Ping Huang
Chao-Ping Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105723Abstract: A semiconductor substrate with an original semiconductor surface (OSS); a first gate region; a first concave formed in the semiconductor substrate and below the original semiconductor surface; a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and a first conductive region formed in the first concave and including a first doping region and a second doping region. Wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.Type: ApplicationFiled: September 21, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun LU, Li-Ping HUANG
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Publication number: 20240107746Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Li-Ping HUANG, Wen-Hsien Tu
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Publication number: 20240105846Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Li-Ping HUANG, Wen-Hsien Tu
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Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 10644181Abstract: A photovoltaic module is provided, and a cell set thereof includes a first cell, a second cell, and a conductive connection element. In the first cell, a first semiconductor stack has a first surface, a second surface, and a first side surface. A first electrode is disposed on the first surface. A second electrode is disposed on the second surface. In the second cell, a second semiconductor stack has a third surface, a fourth surface, and a second side surface. A third electrode is disposed on the third surface. A fourth electrode is disposed on the fourth surface. The conductive connection element connects the first electrode with a part of a first insulation layer on the second surface, and connects the third electrode with a part of a second insulation layer on the fourth surface.Type: GrantFiled: November 30, 2017Date of Patent: May 5, 2020Assignee: Industrial Technology Research InstituteInventors: Chao-Ping Huang, Shang-Yeh Wen, Cheng-Yu Peng
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Publication number: 20190051782Abstract: A photovoltaic module is provided, and a cell set thereof includes a first cell, a second cell, and a conductive connection element. In the first cell, a first semiconductor stack has a first surface, a second surface, and a first side surface. A first electrode is disposed on the first surface. A second electrode is disposed on the second surface. In the second cell, a second semiconductor stack has a third surface, a fourth surface, and a second side surface. A third electrode is disposed on the third surface. A fourth electrode is disposed on the fourth surface. The conductive connection element connects the first electrode with a part of a first insulation layer on the second surface, and connects the third electrode with a part of a second insulation layer on the fourth surface.Type: ApplicationFiled: November 30, 2017Publication date: February 14, 2019Applicant: Industrial Technology Research InstituteInventors: Chao-Ping Huang, Shang-Yeh Wen, Cheng-Yu Peng
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Patent number: 8970271Abstract: A signal coupling circuit for generating an output signal according to an input signal is provided. The signal coupling circuit includes: a coupling capacitor, configured to generate a coupling signal according to the input signal; a clock generating circuit, configured to generate a clock and determine a duty cycle of the clock by the coupling capacitor; a discharge circuit, configured to intermittently discharge the coupling capacitor according to the duty cycle of the clock; and an output circuit, coupled to the coupling capacitor, for generating the output signal according to the coupling signal.Type: GrantFiled: December 23, 2013Date of Patent: March 3, 2015Assignee: MStar Semiconductor, Inc.Inventors: Chao-Chun Sung, Chao-Ping Huang, Chien-Hung Chen, Chu-Wei Hsia
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Publication number: 20140176211Abstract: A signal coupling circuit for generating an output signal according to an input signal is provided. The signal coupling circuit includes: a coupling capacitor, configured to generate a coupling signal according to the input signal; a clock generating circuit, configured to generate a clock and determine a duty cycle of the clock by the coupling capacitor; a discharge circuit, configured to intermittently discharge the coupling capacitor according to the duty cycle of the clock; and an output circuit, coupled to the coupling capacitor, for generating the output signal according to the coupling signal.Type: ApplicationFiled: December 23, 2013Publication date: June 26, 2014Applicant: MStar Semiconductor, Inc.Inventors: Chao-Chun Sung, Chao-Ping Huang, Chien-Hung Chen, Chu-Wei Hsia
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Publication number: 20110022976Abstract: A user interface system for operating software on a computer includes a pointing device operable by a user's primary dexterous hand, a keyboard operable by the user's secondary dexterous hand, a matrix of keyboard keys on the keyboard. The matrix may include a first set of functions that are selected from a plurality of functions, and can be programmed to the matrix and displayed on the computer screen as a context menu. The selection of the functions being programmed to the matrix is dynamically linked to a previously executed function.Type: ApplicationFiled: October 1, 2010Publication date: January 27, 2011Applicant: CADexterity, Inc.Inventors: Chao-Ping Huang, Sheng-Chun Yuan
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Patent number: 7741987Abstract: An analog circuit architecture is fabricated with dual gate oxides and dual voltage supplies. In the analog circuit architecture, different kinds of devices/transistors with different gate oxide thicknesses are biased by different voltages, such that advantages of each device technology are mixed to enhance total performance of the analog circuit. For example, thin oxide 0.18 um transistors are biased at 1.8V for higher speed and lower power consumption, whereas thick oxide 0.35 um transistors are biased at 3.3V for a wider signal swing range.Type: GrantFiled: December 5, 2008Date of Patent: June 22, 2010Assignee: MStar Semiconductor, Inc.Inventors: Henry Tin-Hang Yung, Chao-Ping Huang, Steve Wiyi Yang
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Patent number: 7598950Abstract: A display control device includes a controller, a scaling engine, a timing controller, a selector and an interface circuit. The controller is for providing a mode-control signal. The scaling engine is for producing a first interface signal. The timing controller is for converting the first interface signal into a second interface signal. The selector selects either the first interface signal or the second interface signal to serve as a reference signal according to the mode-control signal. The interface circuit converts the reference signal into an output signal according to the mode-control signal. When the mode-control signal is under a first mode, the output signal is virtually the first interface signal. When the mode-control signal is under a second mode, the output signal is virtually the second interface signal. When the mode-control signal is under a third mode, the interface circuit converts the first interface signal into a third interface signal to serve as the output signal.Type: GrantFiled: January 31, 2007Date of Patent: October 6, 2009Assignee: MStar Semiconductor, Inc.Inventors: Chih-Tien Chang, Teng-Hann Huang, Chao-Ping Huang
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Publication number: 20090079604Abstract: An analog circuit architecture is fabricated with dual gate oxides and dual voltage supplies. In the analog circuit architecture, different kinds of devices/transistors with different gate oxide thicknesses are biased by different voltages, such that advantages of each device technology are mixed to enhance total performance of the analog circuit. For example, thin oxide 0.18 um transistors are biased at 1.8V for higher speed and lower power consumption, whereas thick oxide 0.35 um transistors are biased at 3.3V for a wider signal swing range.Type: ApplicationFiled: December 5, 2008Publication date: March 26, 2009Inventors: HENRY TIN-HANG YUNG, CHAO-PING HUANG, Steve Wiyi Yang
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Publication number: 20080320418Abstract: The present invention offers an improved GUI interface for CAD software to allow users easy access to menus. A user can execute commands and options with little disruption and with minimal hand movement. The keypad is represented on the computer screen and is called a GUFI (Graphical User Friendly Interface) keypad system. The keypad is a menu having a matrix of graphical buttons. A user selects a computer resource with a spatial input device and clicks the proper context button, the GUFI keypad displays only the functions or commands that pertain to the computer resource selected. The unique GUFI keypad system displays functions and commands in an arrayed, not in a pop-up or pull down menu, but in a pattern relating to the keys on the keyboard. Menu items are accessed through a one to one correspondence with the represented keys mapped to similar physically represented keys.Type: ApplicationFiled: June 21, 2007Publication date: December 25, 2008Applicant: CADexterity, Inc.Inventors: Chao-Ping Huang, Sheng-Chun Yuan
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Patent number: 7274361Abstract: A display control device includes a controller, a scaling engine, a timing controller, a selector and an interface circuit. The controller is for providing a mode-control signal. The scaling engine is for producing a first interface signal. The timing controller is for converting the first interface signal into a second interface signal. The selector selects either the first interface signal or the second interface signal to serve as a reference signal according to the mode-control signal. The interface circuit converts the reference signal into an output signal according to the mode-control signal. When the mode-control signal is under a first mode, the output signal is virtually the first interface signal. When the mode-control signal is under a second mode, the output signal is virtually the second interface signal. When the mode-control signal is under a third mode, the interface circuit converts the first interface signal into a third interface signal to serve as the output signal.Type: GrantFiled: September 26, 2003Date of Patent: September 25, 2007Assignee: MStar Semiconductor, Inc.Inventors: Chih-Tien Chang, Teng-Hann Huang, Chao-Ping Huang
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Publication number: 20070126726Abstract: A display control device includes a controller, a scaling engine, a timing controller, a selector and an interface circuit. The controller is for providing a mode-control signal. The scaling engine is for producing a first interface signal. The timing controller is for converting the first interface signal into a second interface signal. The selector selects either the first interface signal or the second interface signal to serve as a reference signal according to the mode-control signal. The interface circuit converts the reference signal into an output signal according to the mode-control signal. When the mode-control signal is under a first mode, the output signal is virtually the first interface signal. When the mode-control signal is under a second mode, the output signal is virtually the second interface signal. When the mode-control signal is under a third mode, the interface circuit converts the first interface signal into a third interface signal to serve as the output signal.Type: ApplicationFiled: January 31, 2007Publication date: June 7, 2007Inventors: Chih-Tien Chang, Teng-Hann Huang, Chao-Ping Huang
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Multiple Gate Oxide Analog Circuit Architecture With Multiple Voltage Supplies and Associated Method
Publication number: 20070120726Abstract: An analog circuit architecture with dual gate oxides and dual voltage supplies and associated method is provided. In the analog circuit architecture, different kinds of devices/transistors with different gate oxide thicknesses are powered by different voltages, such that advantages of each device technology are mixed to enhance total performance of the analog circuit. For example, thin gate oxide 0.18 um transistors are powered by 1.8V for high speed and low power consumption, whereas thick gate oxide 0.35 um transistors are powered by 3.3V for a wider signal swing range.Type: ApplicationFiled: September 27, 2006Publication date: May 31, 2007Inventors: HENRY TIN-HANG YUNG, CHAO-PING HUANG, STEVE WIYI YANG -
Patent number: 7106231Abstract: A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.Type: GrantFiled: October 27, 2004Date of Patent: September 12, 2006Assignee: MStar Semiconductor, Inc.Inventors: Sterling Smith, Chia-Ming Yang, Chao-Ping Huang, Horng-Der Chang, Henry Tin-Hang Yung
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Publication number: 20050093722Abstract: A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.Type: ApplicationFiled: October 27, 2004Publication date: May 5, 2005Inventors: Sterling Smith, Chia-Ming Yang, Chao-Ping Huang, Horng-Der Chang, Henry Yung
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Publication number: 20050068309Abstract: A display control device includes a controller, a scaling engine, a timing controller, a selector and an interface circuit. The controller is for providing a mode-control signal. The scaling engine is for producing a first interface signal. The timing controller is for converting the first interface signal into a second interface signal. The selector selects either the first interface signal or the second interface signal to serve as a reference signal according to the mode-control signal. The interface circuit converts the reference signal into an output signal according to the mode-control signal. When the mode-control signal is under a first mode, the output signal is virtually the first interface signal. When the mode-control signal is under a second mode, the output signal is virtually the second interface signal. When the mode-control signal is under a third mode, the interface circuit converts the first interface signal into a third interface signal to serve as the output signal.Type: ApplicationFiled: September 26, 2003Publication date: March 31, 2005Inventors: Chih-Tien Chang, Teng-Hann Huang, Chao-Ping Huang