Multiple Gate Oxide Analog Circuit Architecture With Multiple Voltage Supplies and Associated Method

Abstract

An analog circuit architecture with dual gate oxides and dual voltage supplies and associated method is provided. In the analog circuit architecture, different kinds of devices/transistors with different gate oxide thicknesses are powered by different voltages, such that advantages of each device technology are mixed to enhance total performance of the analog circuit. For example, thin gate oxide 0.18 um transistors are powered by 1.8V for high speed and low power consumption, whereas thick gate oxide 0.35 um transistors are powered by 3.3V for a wider signal swing range.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 60/597,390, filed Nov. 29, 2005, and is included herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit architectures, and particularly, to an analog integrated circuit fabrication architecture with multiple gate oxide thicknesses and multiple power voltages, and associated method.

2. Description of the Prior Art

In a modern information society, electronics are used to process, transmit, and receive all kinds of audio and video media. Thus, research in electronics has focused on all kinds of circuits and architectures for processing multimedia electronic signals. Typically, signal processing circuits are categorized by digital circuits and analog circuits. Though the development of new digital circuits is rapid, the importance of analog circuits (including mixed-signal circuits) increases every day. For example, in order to digitize audio and video signals with high quality and low loss, a high-performance, high-speed analog-to-digital converter (ADC) which is one type of analog (mixed-signal) circuit is required. Likewise, electronic signals that are transmitted at high speeds (such as high-speed wireless internet signals) and electronic signals accessed from storage devices (such as a disc), all require processing by analog or mixed-signal circuits. In fact, all signals, regardless of being classified as digital or analog, are substantially analog signals, and analog electronic circuits are able to control the analog portions of electronic signals. Thus, developing high-performance, high-speed analog circuits and architectures is a major concern of modern information technology companies.

Digital signals can carry different information with different signal amplitudes. For example, if the signal amplitude is in a low range, then the information represents “0”, whereas if the signal amplitude is in a high range, the information represents “1”. On the other hand, the amplitude of analog signals represents unique information. Information carried in the analog signal also changes as the signal amplitude of the analog signal varies between low and high. Thus, analog circuits stress an ability to process signals with a large signal swing. In other words, analog circuits should be able to accommodate a large signal swing, so as to process the information in the analog signal. Of course, a critical limiting factor in achieving large signal swing analog circuits is a power voltage of the analog circuit. Typically, the larger the power voltage of the analog circuit is, the larger the allowable signal swing becomes. Thus, in the prior art, analog circuits are powered by a higher voltage than digital circuits to supply the large signal swing.

Generally speaking, circuits powered by high voltages require thick-gate-oxide metal-oxide-semiconductor (MOS) transistors. Thick-gate-oxide devices are able to withstand a high power voltage environment. However, thick-gate-oxide devices have disadvantages when used in analog circuits. Thick-gate-oxide devices are slow, occupy a larger area, and consume more power. In order to improve circuit speeds, the industry has tried to introduce scaled down thin-gate-oxide devices, such as thin-gate-oxide MOS transistors, to analog circuit architectures. These thin-gate-oxide devices are faster, occupy a smaller layout area, and consume less power.

FIG. 1 shows a block diagram of an analog circuit architecture of the prior art, a dual gate-oxide analog-to-digital converter (ADC) 100 with a single power voltage (such as 3.3V). Most devices in the architecture are thick-gate-oxide devices suited to the high power voltage environment, such as 3.3V 0.35 um MOS transistors. A first circuit 120 and a second circuit 140 are both formed of thick-gate-oxide devices of this type. To make up for the relatively slow speed of the thick-gate-oxide devices, the prior art also applies few thin-gate-oxide devices, such as 0.18 um MOS transistors. A third circuit 160 comprises a few such thin-gate-oxide devices.

Although the circuit architecture of FIG. 1 attempts to introduce the few thin-gate-oxide devices, as noted, the thin-gate-oxide transistors can only be applied in low power voltage environments. For example, a gate oxide layer of the thin-gate-oxide transistors is thinner, and cannot withstand large signals in a high power voltage environment, but can only be used in a relatively low power voltage environment. However, as shown in FIG. 1, because the circuit architecture of the prior art only provides the single power voltage, when the thin-gate-oxide devices are fabricated, these thin-gate-oxide transistors must be protected by thick-gate-oxide devices, and cannot be connected directly to the high power voltage. In other words, 0.18 um thin-gate-oxide devices, typically powered by 1.8V, cannot be directly connected to 3.3V. Instead, the 0.18 um thin-gate-oxide devices can only operate normally in the prior art with protection from the 0.35 um devices. Thus, in the prior art, the application and the effectiveness of thin-gate-oxide devices is limited in analog IC design.

SUMMARY OF THE INVENTION

The present invention discloses a multiple power, multi-gate-oxide analog circuit architecture. The architecture comprises a plurality of first devices powered by a first voltage, and a plurality of second devices powered by a second voltage, the second voltage substantially different from the first voltage. For example, the first devices are thin-gate-oxide transistors, such as 0.18 um devices, and the first voltage is a low voltage, such as 1.8V. The second devices are thick-gate-oxide transistors, such as 0.35 um devices, and the second voltage is a high voltage, such as 3.3V. In other words, the first devices are 0.18 um thin-gate-oxide metal-oxide-semiconductor (MOS) transistors fabricated according to a 0.18 um standard. And, the second devices are thick-gate-oxide MOS transistors complying with a 0.35 um standard, but are fabricated in the same process with the first devices, at different steps in the process.

The present invention also discloses a signal processing circuit comprising a plurality of pipeline modules. Each pipeline module comprises a plurality of first devices powered by a first voltage and a plurality of second devices powered by a second voltage, the second voltage being substantially different from the first voltage. As described above, the first devices are thin-gate-oxide transistors, such as 0.18 um devices, powered by 1.8V, and the second devices are thick-gate-oxide transistors, such as 0.35 um devices, powered by 3.3V.

The present invention also discloses a method of realizing, including designing and fabricating, an analog circuit. First, a plurality of different devices is realized in the analog circuit. The different devices are powered by different voltage sources. For example, in a 0.18 um process, 0.35 um devices (thick-gate-oxide transistors) could be fabricated first, and 0.18 um devices (thin-gate-oxide transistors) could be fabricated second. 3.3V and 1.8V are provided for the 0.35 um devices and the 0.18 um devices, respectively.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an analog-to-digital converter in an analog circuit architecture according to the prior art.

FIG. 2 is a diagram of an analog circuit architecture according to the present invention.

FIG. 3 is a circuit block diagram of the analog circuit architecture according to the present invention.

FIG. 4 is a diagram of an analog-to-digital converter in the analog circuit architecture according to the present invention.

FIG. 5 is a diagram of two different configurations for providing different power voltages to different gate oxide thickness devices in the analog circuit architecture according to the present invention.

FIG. 6 is a flow chart of a method of realizing an analog integrated circuit according to the preferred embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2, which is a diagram of an analog circuit 200 according to the present invention architecture. The analog circuit 200 comprises a plurality of transistors with different oxide thicknesses, and provides multiple power voltages for each type of transistor. The analog circuit 200 comprises thick-gate-oxide devices and thin-gate-oxide devices. Corresponding to the two device types, the analog circuit 200 provides two different power voltages. A low power voltage biases a circuit 240 comprising the thin-gate-oxide devices, while a high power voltage biases a circuit 220 comprising the thick-gate-oxide devices. Alternatively, the circuit 220 comprises a plurality of thin-gate-oxide devices and a plurality of thick-gate-oxide devices. According to the powering scheme of the present invention, the circuit 240 provides high speed and low power consumption by the thin-gate-oxide devices, and provides a high signal swing range by the thick-gate-oxide devices.

In this embodiment, the thin-gate-oxide MOS transistors of FIG. 2 could be 0.18 um devices, which can be powered by the low power voltage of 1.8V. With this low power voltage, the 0.18 um devices can be directly coupled to the 1.8V voltage source to draw power, without coupling to the thick-gate-oxide devices for indirectly drawing electrical power. Thus, the analog circuit architecture of the present invention can employ a greater number of thin-gate-oxide devices to improve the overall effectiveness of the analog circuit, increasing speed, lowering power consumption, shrinking layout area, and improving device integration. Likewise, the thick-gate-oxide devices can be 0.35 um devices, such as thick-gate-oxide MOS transistors, fabricated in a 0.18 um process, and directly powered by the high power voltage of 3.3V. With this high power voltage, the analog circuit using the thick-gate-oxide devices tolerates signals with higher swing range.

Please refer to FIG. 3, which shows an analog circuit architecture of the present invention. An analog circuit 300 comprises a logic block 340, comprising logic gates, such as inverters, which are formed preferably of thin-gate-oxide devices, such as 0.18 um transistors. The thin-gate-oxide devices are powered by a low power voltage of 1.8V. Blocks with analog functions, such as a circuit 320, comprise thick-gate-oxide transistors mixed with thin-gate-oxide transistors. Likewise, these pipeline modules 320 use a mix of the high power voltage (3.3V) and the low power voltage (1.8V) to appropriately bias the thick-gate-oxide transistors and the thin-gate-oxide transistors, respectively. For example, the circuit 320 comprises an analog amplifier, such as a differential amplifier or an operational amplifier. A front end of the amplifier can be formed of thin-gate-oxide devices and powered by the low power voltage, whereas later stages of the amplifier can be formed of thick-gate-oxide devices and powered by the high power voltage. In this manner, the amplifier can handle both high speed and large output signal swing.

As seen from the discussion of FIG. 3, the present invention not only uses thin-gate-oxide devices with a low power voltage in a logic section of an analog circuit, but also makes appropriate use of a few thin-gate-oxide devices with the low power voltage in analog blocks, such as the amplifier mentioned above. This improves the performance of the analog circuit according to the present invention, such as higher speed and less power consumption, without sacrificing high signal swing.

The analog circuit of FIG. 3 can be an analog-to-digital converter (ADC). For a more detailed description of how to apply the present invention architecture to develop a high-performance ADC, please refer to FIG. 4. FIG. 4 shows a pipeline ADC 400 as an example. The pipeline ADC 400 comprises a plurality (stage 1 through stage N) of pipeline modules 410 connected in series. Each pipeline module 410 can receive an input signal, generate an output signal by processing the input signal, and output the output signal. Aj-th pipeline module 410 receives an analog signal from the pipeline module 410 preceding the j-th pipeline module 410, and outputs a processed analog signal to the pipeline module 410 following the j-th pipeline module 410. An analog input signal Vin is processed by the first pipeline module 410. Each pipeline module 410 comprises a sample/hold (S/H) circuit 510, an ADC module 520, a digital-to-analog converter (DAC) module 530, a synthesizer 540, and an output amplifier 550. The S/H circuit 510 is an input circuit of the pipeline module 410, and samples the analog output signal from the pipeline module 410 directly preceding in the series. The ADC module 520, the DAC module 530, and the synthesizer 540 together form a core circuit. The resulting sample of the S/H circuit 510 is converted into a K+1 bit digital signal Sd(j) by the ADC module 520, wherein K is a constant. The digital signal Sd(j) is then converted into an analog signal Sao) by the DAC module 530. Finally, the synthesizer 540, which can be an adder, subtracts the output of the S/H circuit 510 and the analog signal Sa(j). The output signal of the synthesizer 540 is sent to a next pipeline module 410 through the output amplifier 550, which is considered an output circuit of the pipeline module 410.

The ADC 400 further comprises a plurality of delay circuits 420 corresponding to each pipeline module 410. Each delay circuit 420 delays the digital signal of the corresponding pipeline module 410, and sends the delayed signal to an error correction circuit 430. According to the plurality of delay signals from the delay circuits 420, the digital error correction circuit 430 outputs a digital value representing a magnitude of the analog input signal Vin.

Implementing the ADC 400 according to one embodiment of the present invention, the delay circuits 420 and the error correction circuit 430 preferably apply thin-gate-oxide devices, such as 0.18 um thin-gate-oxide transistors powered by 1.8V. For the pipeline modules 410, the S/H circuits 510 and the output amplifiers 550 preferably apply a mix of the thin-gate-oxide devices and the thick-gate-oxide devices. In other words, these two circuits are implemented by mixing different gate oxide thickness devices powered by different powers, such as 0.18 um thin-gate-oxide transistors powered by 1.8V and 0.35 um thick-gate-oxide transistors powered by 3.3V. The core circuit of each pipeline module 410, comprising the ADC module 520, the DAC module 530, and the synthesizer 540, preferably applies the thin-gate-oxide devices, such as 0.18 um thin-gate-oxide transistors powered by 1.8V, and the thin-gate-oxide devices are preferably powered by the low power voltage. In such a manner, the thin-gate-oxide devices exploit the advantages of fast speed and low power consumption. Likewise, the thick-gate-oxide devices powered by the high voltage are able to tolerate and process high signal swing analog signals. Thus, the present invention discloses a high-efficiency, low-power, high performance ADC and other kinds of analog circuits. For example, compared with an ADC of the prior art, the present invention ADC exhibits a 20% increase in processing speed, while consuming 30% less power.

When the present invention architecture is realized in an integrated circuit (IC), different power arrangements can be employed to provide different power voltages for different gate oxide thickness devices, respectively. Please refer to FIG. 5, which shows two different embodiments of a dual power voltage scheme according to the present invention. In a configuration A, the IC can be powered by a plurality of external power source ports, each including power pins, power pads and/or power balls. Each independent port is connected to an independent external power supply, and different gate oxide thickness devices drain their power from the power ports, respectively. Generally speaking, when the IC is disposed on a printed circuit board (PCB), the PCB has a voltage regulator circuit, or a voltage regulator IC thereon, for providing different voltage supplies. So, the IC in the configuration A can have a plurality of power voltages from the external voltage regulator through the power ports. Preferably, the architecture is implemented on a single substrate.

In another configuration B, the IC comprises a single external power port that is connected to a signal external power voltage source. The IC further comprises an internal voltage regulator circuit, which generates a plurality of power voltages from the single external power voltage of the external power port, so as to provide different power voltages for the different gate oxide thickness devices. In the configuration B, a single 3.3V voltage is provided to the IC through the external power port, and the internal voltage regulator circuit uses the 3.3V voltage to further generate other power voltage(s), such as a 1.8V voltage. In this way, the present invention circuit can directly power the thick-gate-oxide 0.35 um devices with the 3.3V voltage, and the thin-gate-oxide 0.18 um devices with a 1.8V voltage through the internal voltage regulator circuit.

FIG. 6 shows a flow chart of implementing an analog integrated circuit according to a preferred embodiment of the present invention. In step 610, a first circuit comprising a plurality of first devices is implemented in an analog integrated circuit (IC). In step 620, a second circuit comprising a plurality of second devices is implemented in the analog IC. The first circuit and the second circuit are powered by different voltages. The first devices and the second devices are fabricated in different fabrication steps in a single fabrication process. For instance, in a 0.18 um process, the first circuit comprises a plurality of 0.18 um devices, the second circuit comprises a plurality of 0.35 um devices, the first circuit is directly powered by 1.8V, and the second circuit is directly powered by 3.3V.

In summary, the present invention discloses an analog circuit architecture in which devices with different gate oxide thicknesses are fabricated in different steps of a single fabrication process, and powered with different corresponding power voltages. In the prior art, an analog circuit is powered by a single high power voltage. In contrast, the present invention analog circuit architecture employs both thick-gate-oxide and thin-gate-oxide devices, biased by different power voltages respectively, so as to remove the limitations on usage of the thin-gate-oxide devices for analog circuits. In this way, the present invention can apply the thin-gate-oxide devices extensively to take advantages of the thin-gate-oxide devices and the thick-gate-oxide devices. Thus, without sacrificing the signal swing, the analog circuit according to the present invention increases operation speed, reduces power consumption and shrinks layout area. A 0.18 um process provides both 0.18 um devices and 0.35 um devices. As described in the above embodiments, the present invention powers the 0.18 um and 0.35 um devices with 1.8V and 3.3V, respectively, thus improving the performance of the analog circuit. As semiconductor processes advance, the present invention applies different gate oxide thickness devices with multiple power voltages to optimize the overall performance of the analog circuit.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A multi-power multi-gate-oxide analog circuit architecture comprising:

a plurality of first devices powered by a first voltage; and

a plurality of second devices powered by a second voltage,

wherein the second voltage is different from the first voltage.

2. The analog circuit architecture of claim 1, wherein the plurality of first devices is in thin-gate-oxide Metal Oxide Semiconductor (MOS) technology, the plurality of second devices is in thick-gate-oxide MOS technology, and the second voltage is higher than the first voltage.

3. The analog circuit architecture of claim 1, wherein the plurality of first devices and the plurality of second devices are fabricated in one process but undergo different process steps.

4. The analog circuit architecture of claim 1, wherein the architecture can process an analog signal.

5. The analog circuit architecture of claim 1, wherein the architecture implements an analog-to-digital converter.

6. The analog circuit architecture of claim 1, wherein the architecture implements a mixed-signal circuit.

7. The analog circuit architecture of claim 1, wherein the architecture is implemented on a single substrate.

8. A pipeline analog-to-digital converter comprising:

a plurality of pipeline modules, each pipeline module comprising a plurality of first devices powered by a first voltage and a plurality of second devices powered by a second voltage,

wherein the second voltage is different from the first voltage.

9. The pipeline analog-to-digital converter (ADC) of claim 8, wherein the ADC is an analog circuit for processing an analog signal.

10. The pipeline analog-to-digital converter of claim 9, wherein each pipeline module comprises an input circuit, an output circuit and a core circuit, the input circuit and the output circuit are formed of a first portion of the first devices and the second devices, and the core circuit is formed of a second portion of the first devices, the input circuit and the output circuit respectively receive and transmit a high-swing signal, and the core circuit is connected between the input circuit and the output circuit for signal processing of the high-swing signal received from the input circuit.

11. The pipeline analog-to-digital converter of claim 8, wherein each pipeline module comprises a sample/hold circuit, an output amplifier and a core circuit, the sample/hold circuit and the output amplifier are formed of a first portion of the first devices and the second devices, and a core circuit is formed of a second portion of the first devices, the sample/hold circuit and the output amplifier receive and transmit a high-swing signal respectively, and the core circuit is connected between the sample/hold circuit and the output amplifier for processing the high-swing signal received from the sample/hold circuit.

12. The pipeline analog-to-digital converter (ADC) of claim 11, wherein the core circuit comprises:

an ADC module for generating a digital signal based on an output signal from the sample/hold circuit;

a digital-to-analog converter (DAC) for converting the digital signal to an analog signal; and

a synthesizer for synthesizing the analog signal and the output signal of the sample/hold circuit.

13. The pipeline analog-to-digital converter of claim 11 further comprising:

a plurality of delay circuits corresponding to the plurality of pipeline modules, each delay circuit delaying a digital signal from the corresponding pipeline module; and

a digital error correction circuit for generating a digital output signal according to the delayed digital signals of the delay circuits.

14. The pipeline analog-to-digital converter of claim 13, wherein each delay circuit and the error correction circuit are formed of a plurality of the first devices.

15. The pipeline analog-to-digital converter of claim 8, wherein the first devices are thin-gate-oxide metal-oxide-semiconductor (MOS) transistors, the second devices are thick-gate-oxide MOS transistors, and the second voltage is higher than the first voltage.

16. The pipeline analog-to-digital converter of claim 8, wherein the first devices and the second devices are formed in one process but undergo different process steps.

17. The pipeline analog-to-digital converter of claim 8, wherein the pipeline analog-to-digital converter is implemented on a single substrate.

18. A method of fabricating an analog integrated circuit (IC), the method comprising:

fabricating a first circuit in the analog IC; and

fabricating a second circuit in the analog IC,

wherein the first circuit and the second circuit are powered by a first power voltage and a second power voltage respectively, and the first power voltage and the second power voltage are different.

19. The method of claim 18, wherein the first power voltage is lower than the second power voltage.

20. The method of claim 18, wherein the first circuit comprises a plurality of first devices and the second circuit comprises a plurality of second devices.

21. The method of claim 20, wherein the first circuit and the second circuit are fabricated with different gate oxide thickness.