Patents by Inventor Chao Su

Chao Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240423118
    Abstract: A planter suitable for block seeds that relates to the technical field of agricultural seeding machinery is disclosed. The planter includes a frame, a fertilizing tank, a fertilizing box, a seeding mechanism, a control mechanism, a seed box, a ridging mechanism, land wheels, a seeding furrower, a fertilizing furrower, a seed-clearing mechanism, and a replanting mechanism. The fertilizing tank, the fertilizing furrower, the fertilizing box, the seeding furrower, the seeding mechanism, the land wheels, the control mechanism, the seed box, and the ridging mechanism are mounted in turn from one end to the other end of the frame. A photoelectric sensor of an active infrared intrusion detector is adopted to dynamically monitor the presence of the seed potatoes on a seed-discharge spoon in a conveying process. Seeds are replanted with the control mechanism when the seeds are sowed with an empty spoon.
    Type: Application
    Filed: December 28, 2022
    Publication date: December 26, 2024
    Inventors: MIN LIAO, CHAO SU, JIE YANG, RUI CHEN, YU ZHANG, XIUYIN LI, XIAOFENG GAN, RUHU DENG, HU YANG, JUNJU LI, HAILONG XIA, JIARUI WANG
  • Patent number: 12040019
    Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fu-Chen Chang, Chu-Jie Huang, Nai-Chao Su, Kuo-Chi Tu, Wen-Ting Chu
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 11900586
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240011044
    Abstract: The present invention provides novel DNA molecules and constructs, including their nucleotide sequences, useful for modulating gene expression in plants and plant cells. The invention also provides transgenic plants, plant cells, plant parts, seeds, and commodity products comprising the DNA molecules operably linked to heterologous transcribable polynucleotides, along with methods of their use.
    Type: Application
    Filed: July 4, 2023
    Publication date: January 11, 2024
    Inventors: Thomas Ott, Chao Su
  • Publication number: 20230360390
    Abstract: The present disclosure provides a transmission line defect identification method based on a saliency map and a semantic-embedded feature pyramid, including the following steps: step 1: cleaning and classifying a dataset; step 2: generating a super-resolution image for a small target of a transmission line by using an Electric Line-Enhanced Super-Resolution Generative Adversarial Network (EL-ESRGAN) model; step 3: performing image saliency detection on the dataset by constructing a U2-Net; step 4: performing data augmentation on the dataset by using GridMask and random cutout algorithms based on a saliency map, and generating a classified dataset; and step 5: performing image classification on a normal set and a defect set by using a ResNet34 classification algorithm and a deep semantic embedding (DSE)-based feature pyramid classification network.
    Type: Application
    Filed: December 14, 2022
    Publication date: November 9, 2023
    Inventors: Qiang Yang, Chao Su, Yuan Cao, Di Jiang, Hao Xu, Kaidi Qiu
  • Patent number: 11769005
    Abstract: Techniques are provided for assessing uniqueness of information using string-based collection frequency techniques. One method comprises obtaining multiple collections of documents from at least one data source; determining a collection frequency for a given character string based on a number of the collections comprising the given character string relative to a total number of the collections; assigning a uniqueness rating to the given character string based at least in part on a comparison of the collection frequency of the given character string to a collection frequency of one or more additional character strings in one or more of the plurality of collections; and performing an automated action using the given character string based on the assigned uniqueness rating. The automated action may comprise protecting the given character string and/or identifying the given character string as important information satisfying one or more importance criteria.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 26, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Shou-Huey Jiang, Wenjin Liu, Chao Su
  • Publication number: 20230274780
    Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: Fu-Chen Chang, Chu-Jie Huang, Nai-Chao Su, Kuo-Chi Tu, Wen-Ting Chu
  • Patent number: 11682456
    Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fu-Chen Chang, Chu-Jie Huang, Nai-Chao Su, Kuo-Chi Tu, Wen-Ting Chu
  • Publication number: 20230166777
    Abstract: The invention relates to a bogie for a rail vehicle characterized by a high lightweight construction potential. The bogie (1, 1*, 1**) according to the invention has, for primary suspension, a torsion spring system (12) in the inner volume of which a roll stabilizer having a torsion rod (11) is arranged in a torsionally movable manner. The roll stabilizer can be articulated to the car body of the rail vehicle or to the torsion spring system (12). The bogie (1, 1*, 1**) according to the invention advantageously has a particularly large installation space for built-in components.
    Type: Application
    Filed: March 29, 2021
    Publication date: June 1, 2023
    Applicants: CRRC QINGDAO SIFANG CO., LTD., CG RAIL - CHINESISCH-DEUTSCHES FORSCHUNGS- UND ENTWICKLUNGSZENTRUM FÜR BAHN
    Inventors: Andreas ULBRICHT, Werner HUFENBACH, Florian ZEIDLER, Sansan DING, Zhenxian ZHANG, Yulong GAO, Xiongfei ZHANG, Dawei RUAN, Chao SU, Kejian LIU, Xin CAO
  • Publication number: 20230160779
    Abstract: An apparatus, system and method for testing a micro-optical component system. The apparatus, system and method may include a receiver for receiving the micro optical component system; a light source; and a coupler for passing aspects of light from the light source through the micro optical component system to a termination, and for passing remaining aspects from the light source back reflected from the micro optical component system to a power meter. A reading at the power meter of the back reflection may correspond to a diagnosis of the micro optical component system.
    Type: Application
    Filed: April 13, 2021
    Publication date: May 25, 2023
    Applicant: JABIIL INC.
    Inventors: GUAN WEIHUA, WILLIAM STERLING, CHAO SU
  • Publication number: 20230086871
    Abstract: The present invention provides novel DNA molecules and constructs, including their nucleotide sequences, useful for modulating gene expression in plants and plant cells. The invention also provides DNA molecules and constructs, including their nucleotide sequences, useful for expressing proteins in plants to promote symbiotic infection. The invention also provides plants and plant cells transgenic plants, plant cells, plant parts, seeds, and commodity products comprising the DNA molecules operably linked to heterologous transcribable polynucleotides, along with methods of their use.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 23, 2023
    Inventors: Thomas Ott, Lina Siukstaite, Chao Su, Winfried Römer
  • Publication number: 20230062850
    Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.
    Type: Application
    Filed: August 28, 2021
    Publication date: March 2, 2023
    Inventors: Fu-Chen CHANG, Chu-Jie HUANG, Nai-Chao SU, Kuo-Chi TU, Wen-Ting CHU
  • Patent number: 11461676
    Abstract: Methods, apparatus, and processor-readable storage media for implementing a machine learning-based recommendation engine for storage system usage within an enterprise are provided herein. An example computer-implemented method includes processing input data pertaining to multiple storage systems within an enterprise; determining association rules applicable to the multiple storage systems by applying machine learning techniques to the processed input data; generating configuration-related recommendations applicable to one or more of the storage systems by applying content filtering techniques to the determined association rules; and outputting, via user interfaces, the configuration-related recommendations to a user for use in connection with storage system configuration actions and/or an entity within the enterprise for use in connection with user-support actions.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 4, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Bina K. Thakkar, Roopa A. Luktuke, Chao Su, Aditya Krishnan, Deepak Gowda
  • Patent number: 11341514
    Abstract: Methods, apparatus, and processor-readable storage media for determining user retention values using machine learning and heuristic techniques are provided herein. An example computer-implemented method includes processing multiple forms of input data pertaining to interactions between a user and an enterprise; generating one or more user sentiment values from the processed input data by applying machine learning techniques to the processed input data; determining a user-specific estimate for the enterprise retaining the user, wherein determining the user-specific estimate comprises combining the one or more sentiment values with one or more storage system heuristics-based values derived from enterprise-related data; and outputting the user-specific estimate to at least one entity within the enterprise for use in connection with user-support actions.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 24, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Bina K. Thakkar, Chao Su, Roopa A. Luktuke, Aditya Krishnan, Deepak Gowda
  • Publication number: 20210374336
    Abstract: Techniques are provided for assessing uniqueness of information using string-based collection frequency techniques. One method comprises obtaining multiple collections of documents from at least one data source; determining a collection frequency for a given character string based on a number of the collections comprising the given character string relative to a total number of the collections; assigning a uniqueness rating to the given character string based at least in part on a comparison of the collection frequency of the given character string to a collection frequency of one or more additional character strings in one or more of the plurality of collections; and performing an automated action using the given character string based on the assigned uniqueness rating. The automated action may comprise protecting the given character string and/or identifying the given character string as important information satisfying one or more importance criteria.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Shou-Huey Jiang, Wenjin Liu, Chao Su
  • Publication number: 20210351097
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.
    Type: Application
    Filed: April 27, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Patent number: 11154949
    Abstract: An apparatus, system and method for micro welding, wherein insulated object, such as a wire, that includes a metallic conductor that is at least partially covered by one or more layers of insulation, is positioned across a termination point. A laser beam may be applied to an area of the insulated object overlapping the termination point, wherein the applied laser beam is configured to substantially simultaneously (i) ablate the one or more layers of insulation in a first region of the area, (ii) weld the metallic conductor to the termination point in a second region of the area, and (iii) detach a portion of the object from the termination point in a third region of the area.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: October 26, 2021
    Assignee: JABIL INC.
    Inventors: William Douglas Sterling, Chao Su, Gongen Gu
  • Patent number: 11017852
    Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Patent number: 11011224
    Abstract: A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu