Abstract: The present disclosure relates to a monitoring method, a monitoring system and a control device for a human-body security-inspection device. The monitoring method includes: collecting operation parameters of preset monitoring points in target circuit modules of the human-body security-inspection device; obtaining parameter ranges according to module identifiers of the target circuit modules and monitoring-point identifiers of the preset monitoring points, wherein the parameter ranges are associated with the module identifiers and the monitoring-point identifiers respectively; determining whether the operation parameters are in the parameter ranges respectively, and then determining location information of a fault point according to the module identifiers and the monitoring-point identifiers if any of the operation parameters is not in a corresponding parameter range.

Abstract: A method for measuring mechanical parameters of a multilayer composite thin film structure and belongs to the technical field of online tests of micro-electro-mechanical system (MEMS for short) material parameters. Equivalent Young modulus and equivalent residual stress of each layer of the multilayer composite thin film structure can be obtained in one step by means of solving an equation set on the basis of a relationship between first-order resonance frequency of multilayer composite fixed-fixed beams and multilayer composite cantilever beams and parameters such as material characteristics and structure size, the online test of multilayer thin film materials can be realized, the test structure and calculating method are simple, and the accuracy is higher. The present invention further discloses a device for measuring mechanical parameters of the multilayer composite thin film structure.

Abstract: A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.

Abstract: A method of judging lack-of-freon in an air conditioner and an air conditioner control method. The control method includes: acquiring outflow air temperatures at the first air outlet and the second air outlet, and calculating a temperature difference; comparing the temperature difference with a preset temperature difference threshold; and adjusting an opening degree of the expansion valve accordingly. In the method, the opening degree of the expansion valve can be automatically adjusted according to a result of temperature comparison to compensate for the flow rate of freon, so as to improve the cooling or heating efficiency of the air conditioning system and realize the adaptive adjustment of the air conditioner, thereby ensuring the cooling or heating efficiency of the system even if the system lacks freon to a slight extent and effectively reducing energy consumption. The judging method has a higher accuracy of judging result, and is easier to implement.

Abstract: Disclosed is a capability test method based on a joint test support platform. The method includes steps of describing an initial capability in a test, combining a capability to be developed based on the initial capability, and determining an evaluation strategy and a joint task background information of the test. Further, the method includes generating a logical shooting range for the joint test support platform according to the joint task background information, developing a test scenario according to the joint task background information and the logical shooting range, decomposing the test scenario, determining a test plan corresponding to the test scenario, executing the test according to the test plan, analyzing and evaluating a test result of the test, and generating one or more joint capability evaluation reports for the test.

Abstract: A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.

Abstract: In some implementations, the present disclosure relates to a method. The method includes obtaining a set of weights for a neural network comprising a plurality of nodes and a plurality of connections between the plurality of nodes. The method also includes identifying a first subset of weights and a second subset of weights based on the set of weights. The first subset of weights comprises weights that used by the neural network. The second subset of weights comprises weights that are prunable. The method further includes storing the first subset of weights in a first portion of a memory. A first error correction code is used for the first portion of the memory. The method further includes storing the second subset of weights in a second portion of the memory. A second error correction code is used for the second portion of the memory. The second error correction code is weaker than the first error correction code.

Abstract: Disclosed is a production process for slotting an outer conductor of a leaky cable, through which an integrated production line incorporating a metal strap slotting production line, a metal strap longitudinal coating production line and a sheathing production line is provided. A semi-finished product from a leaky cable insulation process is subsequently processed by laser in a numerical control laser cutting device for cutting out corresponding slot holes in a metal strap to produce a slotted outer conductor. Then the slotted metal strap is embossed, and directly coated on an insulator in a longitudinal coating forming mould of the outer conductor. The final sheathing process is completed in a sheath plastic extruding machine to produce a finished leaky cable product. The processes of the outer conductor of the leaky cable, including the raw material punching, the longitudinal coating forming, and the outer sheathing, are finished at one time.

Abstract: A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. An SCM smallest writable unit for writing data in the SCM is smaller than a secondary memory smallest writable unit for writing data in the secondary memory. An operation instruction is received from the processor to perform an operation on data stored in the secondary memory. The data is loaded from the secondary memory into the SCM for performance of the operation.

Abstract: Systems and methods are disclosed for determining whether data to be written to a memory should be deduplicated. In some implementations, a method is provided. The method includes determining whether data to be written to a memory should be deduplicated based, at least in part, on status information of a controller and media characteristics of the memory, wherein the status information of the controller indicates a level of resources available for a deduplication operation. In response to determining that the data should be deduplicated, determining whether the data is duplicative based on the type of memory the data is being written to.

Abstract: Systems and methods are disclosed for determining whether data to be written to a memory should be deduplicated. In some implementations, a method is provided. The method includes determining whether data to be written to a memory should be deduplicated based, at least in part, on status information of a controller and media characteristics of the memory, wherein the status information of the controller indicates a level of resources available for a deduplication operation. In response to determining that the data should be deduplicated, determining whether the data is duplicative based on the type of memory the data is being written to.

Abstract: A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.

Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure on the semiconductor substrate, at least one first isolation structure, and at least on first drift region. The first isolation structure and the first drift region are disposed in the semiconductor substrate at a side of the gate structure. The first isolation structure vertically penetrates through the first drift region.

Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored a a currant value in a parity page of the parity buffer, the pants page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. Data smaller than a smallest writable unit of the secondary memory is accessed in the SCM based on an instruction from the processor. In another aspect, unique identifiers are calculated for portions of data to be stored in the secondary memory using the portions of data. A mapping of the unique identifiers is stored with indications of physical locations where the corresponding portions of data are stored in the secondary memory. In yet another aspect, an operation instruction is received from the processor, and data is loaded from the secondary memory into the SCM for performing the operation.

Abstract: The present disclosure relates to a multimedia information playing method and system, a standardized server and a live broadcast terminal, and relates to the technical field of networks. The method includes receiving n pieces of multimedia information from the n acquisition devices, respectively, each of the n pieces of multimedia information being obtained by acquiring ambient environmental information by a corresponding acquisition device; receiving a selection instruction from the live broadcast terminal; selecting initial multimedia information from the n pieces of multimedia information based on the selection instruction; and sending the initial multimedia information to the playing terminal that is configured to play the initial multimedia information.

Abstract: The present disclosure relates to presentation of live multimedia information via a live multimedia information system that includes a collecting device, and a standardization server. A live instruction sent by a live terminal is received; ambient information is recorded and multimedia information is obtained using the collecting device; the multimedia information, which may include audiovisual information to be presented in real time to remote viewers, is sent to the standardization server according to the live instruction, which may identify a destination for the multimedia information. The standardization server may send the multimedia information, which may be optimized for one or more playing terminals, to a playing terminal, and the playing terminal may receive and play the multimedia information for a remote audience. Playback quality is improved for live multimedia information.

Abstract: Techniques are presented for efficiently storing deep neural network (DNN) weights or similar type data sets in non-volatile memory. For data sets, such as DNN weights, where the elements are multi-bit values, bits of the same level of significance from the elements of the data set are formed into data streams. For example, the most significant bit from each of the data elements are formed into one data stream, the next most significant bit into a second data stream, and so on. The different bit streams are then encoded with differing strengths of error correction code (ECC), with streams corresponding to more significant bits encoded with stronger ECC code than streams corresponding to less significant bits, giving the more significant bits of the data set elements a higher level of protection.

Abstract: A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. Data smaller than a smallest writable unit of the secondary memory is accessed in the SCM based on an instruction from the processor. In another aspect, unique identifiers are calculated for portions of data to be stored in the secondary memory using the portions of data. A mapping of the unique identifiers is stored with indications of physical locations where the corresponding portions of data are stored in the secondary memory. In yet another aspect, an operation instruction is received from the processor, and data is loaded from the secondary memory into the SCM for performing the operation.