Abstract: A method the following operations: downscaling an input image to generate a scaled image; performing, to the scaled image, a first convolutional neural networks (CNN) modeling process with first non-local operations, to generate global parameters; and performing, to the input image, a second CNN modeling process with second non-local operations that are performed with the global parameters, to generate an output image corresponding to the input image. A system is also disclosed herein.

Abstract: A convolutional neural network processor includes an information decode unit and a convolutional neural network inference unit. The information decode unit is configured to receive a program input and weight parameter inputs and includes a decoding module and a parallel processing module. The decoding module receives the program input and produces an operational command according to the program input. The parallel processing module is electrically connected to the decoding module, receives the weight parameter inputs and includes a plurality of parallel processing sub-modules for producing a plurality of weight parameter outputs. The convolutional neural network inference unit is electrically connected to the information decode unit and includes a computing module. The computing module is electrically connected to the parallel processing module and produces an output data according to an input data and the weight parameter outputs.

Abstract: A deep neural network accelerating method using a plurality of ring tensors includes a plurality of steps. A ring tensor setting step includes setting an input feature ring tensor and a weight ring tensor of a convolutional network. A ring tensor convolution calculating step includes calculating a plurality of input feature ring elements of the input feature ring tensor and a plurality of weight ring elements of the weight ring tensor according to a ring multiplication calculating step and a ring addition calculating step to generate a plurality of convolution feature ring elements of a convolution feature ring tensor. A non-linear tensor activation function calculating step includes executing a directional non-linear activation function on one of the convolution feature ring elements of the convolution feature ring tensor to generate an output feature ring element.

Abstract: A block-based inference method for a memory-efficient convolutional neural network implementation is performed to process an input image. A block-based inference step is performed to execute a multi-layer convolution operation on each of a plurality of input block data to generate an output block data and includes selecting a plurality of ith layer recomputing features according to a position of the output block data along a scanning line feed direction, and then selecting an ith layer recomputing input feature block data according to the position of the output block data and the ith layer recomputing features, and selecting a plurality of ith layer reusing features according to the ith layer recomputing input feature block data along a block scanning direction, and then combining the ith layer recomputing input feature block data with the ith layer reusing features to generate an ith layer reusing input feature block data.

Abstract: A convolutional neural network processor includes an information decode unit and a convolutional neural network inference unit. The information decode unit is configured to receive a program input and weight parameter inputs and includes a decoding module and a parallel processing module. The decoding module receives the program input and produces an operational command according to the program input. The parallel processing module is electrically connected to the decoding module, receives the weight parameter inputs and includes a plurality of parallel processing sub-modules for producing a plurality of weight parameter outputs. The convolutional neural network inference unit is electrically connected to the information decode unit and includes a computing module. The computing module is electrically connected to the parallel processing module and produces an output data according to an input data and the weight parameter outputs.

Abstract: A block-based digital refocusing method includes a capturing step, a dividing step, a selecting step, a refocusing step and a combining step. The capturing step is for capturing at least one picture datum. The dividing step is for dividing the picture datum into a plurality of block data. The selecting step is for defining a regional datum according to each of the block data. The refocusing step is for conducting a refocusing computation to obtain a refocused block datum according to each of the regional data. The combining step is for combining each of the refocused block data based on each of the regional data to form a refocused picture datum.

Abstract: A digital refocusing method includes: a plurality of images corresponding to multiple views in a scene are obtained, the images include a central view image and at least one non-central view image; a pixel shift or a pixel index shift is performed to the non-central view image; a line scan along a pre-determined linear path is performed to the central view image and the non-central view images to obtain corresponding pixels of the central view image and corresponding pixels of the non-central view images; view interpolation based on the disparities defined in a disparity map is performed, target pixels corresponded to a novel view image are obtained from the corresponding pixels of the central view image and the corresponding pixels of the non-central view according to a target disparity; and a refocused novel view image is obtained by averaging and compositing the target pixels of novel views.

Abstract: A digital refocusing method includes: to plurality of images corresponding to multiple views in a scene are obtained, the images include a central view image and at least one non-central view image; a pixel shift or a pixel index shift is performed to the non-central view image; a line scan along a pre-determined linear path is performed to the central view image and the non-central view images to obtain corresponding pixels of the central view image and corresponding pixels of the non-central view images; view interpolation based on the disparities defined in a disparity map is performed, target pixels corresponded to a novel view image are obtained from the corresponding pixels of the central view image and the corresponding pixels of the non-central view according to a target disparity; and a refocused novel view image is obtained by averaging and compositing the target pixels of novel views.

Abstract: A block-based digital refocusing method includes a capturing step, a dividing step, a selecting step, a refocusing step and a combining step. The capturing step is for capturing at least one picture datum. The dividing step is for dividing the picture datum into a plurality of block data. The selecting step is for defining a regional datum according to each of the block data. The refocusing step is for conducting a refocusing computation to obtain a refocused block datum according to each of the regional data. The combining step is for combining each of the refocused block data based on each of the regional data to form a refocused picture datum.

Abstract: The exemplary embodiments of the present invention are direct to a method for generating a resampling reference picture and an apparatus and video decoding system using this method. The video image decoding system is used to decode a bit stream, so as to obtain a current frame. The method for generating a resampling reference picture includes following steps: (a) looking ahead specific information of next x frames of the current frame in the bit stream; (b) determining whether to generate a resampling reference picture according to the specific information of the next x frames.

Abstract: An intra prediction mode selecting method is disclosed. First, a compress profile and a frame resolution of a frame data are received. Next, a plurality of corresponding prediction modes are selected according to the compress profile and the frame resolution, and the selected prediction modes are scheduled for sequentially calculating a plurality of corresponding cost functions. Finally, the cost functions are compared to select one of the prediction modes to serve as a prediction mode of the frame data.

Abstract: An adaptive canonical Huffman decoder including a symbol index generator, a content selector, and a symbol table buffer circuit is illustrated. The content selector outputs a content selection signal. The symbol table buffer circuit reads a corresponding symbol table from a plurality of symbol tables stored in an external memory according to the content selection signal and stores the corresponding symbol table. The symbol index generator stores decoding information of a plurality of encoding tables and selects a corresponding decoding information among all the decoding information according to the content selection signal. Then, the symbol index generator receives a bit stream and decodes the bit stream according to the corresponding decoding information to obtain a symbol index. After that, the symbol table buffer circuit obtains an output symbol from the corresponding symbol table according to the symbol index.

Abstract: A bit rate control circuit for image compression includes a compression unit, a R-value calculation unit, a linear quantization factor (LQF) calculation unit. The compression unit is used to performs a first quantization process on an image based on a default LQF (LQFini) to obtain an initial bits per pixel (bbpini) with an initial number of zero coefficients (Rini). The R-value calculation unit calculates out a target R value (Rtarget) based on the initial bits per pixel (bbpini), the initial number zero coefficients (Rini), and a target bpp (bbptarget). The LQF calculation unit calculates a target LQF (LQFtarget) based on the target R value Rtarget. The LQFtarget can be used to perform a second compression on the image to obtain a compressed image corresponding to the target bpp (bpptarget).

Abstract: A hardware implementation method for concurrently realizing overlap filter and core transform and an operation method thereof are provided. The overlap filter and core transform can be adjusted according to different specifications, processes, and operation frequencies. The hardware implementation method and the operation method thereof adopt a transform-level hardware sharing architecture and multi-port input/output register array, thereby efficiently realizing overlap filter and core transform.

Abstract: A method and an apparatus for generating a coded block pattern for highpass coefficients are provided. The method includes receiving a quantized highpass coefficient (HP), wherein the HP includes a macroblock data; dividing the macroblock into a plurality of blocks; performing lapped transform (LT) operations of two stages on the said block data, concurrently calculating a plurality of coded block patterns of the blocks corresponding to all possible HP prediction directions; performing a calculation to obtain selection information of the HP prediction directions according to lowpass coefficients (LPs) generated through LT operations of the two stages; selecting a corresponding coded block pattern among the said coded block patterns according to the above-mentioned selection information of the HP prediction directions and outputting the selected coded block pattern.

Abstract: A method and an apparatus for cost calculation in decimal motion estimation are provided. The method comprises the following steps. Firstly, perform interpolation on a current block to get an interpolation result of a position corresponding to a decimal motion vector. Secondly, calculate a cost according to data at integer point positions of a reference frame corresponding to the current block and the decimal motion vector, and according to the interpolation result.

Abstract: A picture decoder having a stream buffer, an H.264/AVC decoder, and a processor is provided. The stream buffer stores stream data. The H.264/AVC decoder decodes the stream data and performs an operation on a slice layer specified in the H.264/AVC standard to reorder reference pictures recorded in a reference picture list according to the stream data and generate a plurality of decoded pictures. The processor executes a program to perform an operation on a sequence layer specified in the H.264/AVC standard and mark the decoded pictures.

Abstract: A bit rate control circuit for image compression includes a compression unit, a R-value calculation unit, a linear quantization factor (LQF) calculation unit. The compression unit is used to performs a first quantization process on an image based on a default LQF (LQFini) to obtain an initial bits per pixel (bbpini) with an initial number of zero coefficients (Rini). The R-value calculation unit calculates out a target R value (Rtarget) based on the initial bits per pixel (bbpini), the initial number zero coefficients (Rini), and a target bpp (bbptarget). The LQF calculation unit calculates a target LQF (LQFtarget) based on the target R value Rtarget. The LQFtarget can be used to perform a second compression on the image to obtain a compressed image corresponding to the target bpp (bpptarget).

Abstract: A method for motion estimation and the apparatus thereof are provided. The method for motion estimation uses multi-resolution hierarchial search and allows splitting the optimal block mode at the level of the lowest resolution. The method also allows further splitting of blocks during local refinement at levels of higher resolutions.

Abstract: A data reuse method with level C+ for block matching motion estimation is disclosed. Compared to conventional Level C scheme, this invention can save large external memory bandwidth of motion estimation. The main idea is to reuse the overlapped searching region in the horizontal direction and partially reuse the overlapped searching region in the vertical direction. Several vertical successive current macroblocks are stitched, and the searching region of these current macroblocks is loaded, simultaneously. With the small overhead of internal memory, the reduction of external memory bandwidth is large. By case studies of H.264/AVC, the level C+ scheme can provide a good trade-off between the conventional Level C and D scheme.