Abstract: A data reuse method with level C+ for block matching motion estimation is disclosed. Compared to conventional Level C scheme, this invention can save large external memory bandwidth of motion estimation. The main idea is to reuse the overlapped searching region in the horizontal direction and partially reuse the overlapped searching region in the vertical direction. Several vertical successive current macroblocks are stitched, and the searching region of these current macroblocks is loaded, simultaneously. With the small overhead of internal memory, the reduction of external memory bandwidth is large. By case studies of H.264/AVC, the level C+ scheme can provide a good trade-off between the conventional Level C and D scheme.

Abstract: An image processing apparatus and a method thereof are provided. The image processing apparatus includes a memory device and a first and a second image data transformation unit. A first image data is written into and read from the memory device. Each pixel value has a first data format. The first data format is compatible with a dedicated format accessible by the memory device. The first image data transformation unit transforms a second image data into the first image data. The second image data includes a plurality of pixel values each having a second data format. The second data format is not compatible with the dedicated format. The second image data transformation unit transforms the first image data into a third image data. The third image data includes a plurality of pixel values each having a third data format. The third data format is not compatible with the dedicated format.

Abstract: An intra prediction mode selecting method is disclosed. First, a compress profile and a frame resolution of a frame data are received. Next, a plurality of corresponding prediction modes are selected according to the compress profile and the frame resolution, and the selected prediction modes are scheduled for sequentially calculating a plurality of corresponding cost functions. Finally, the cost functions are compared to select one of the prediction modes to serve as a prediction mode of the frame data.

Abstract: A video processing method and a video processor are disclosed. The video processor includes a processing device, and the video processor is coupled to a buffer. The video processor reads a plurality of current frames to be coded and a plurality of search windows, and performs motion estimation on a plurality of macroblocks (MBs), wherein the MBs are co-located within the current frames to be coded and the current frames to be coded have no data dependence on each other.

Abstract: An apparatus for motion estimation which supports multiple video compression standards and the method thereof is provided. The apparatus uses an interpolation filter with fixed coefficients. The apparatus also adjusts block sizes and calculation details of cost functions according to various video compression standards. Therefore the apparatus is capable of supporting multiple standards and providing high-quality video compression.

Abstract: An adaptive canonical Huffman decoder including a symbol index generator, a content selector, and a symbol table buffer circuit is illustrated. The content selector outputs a content selection signal. The symbol table buffer circuit reads a corresponding symbol table from a plurality of symbol tables stored in an external memory according to the content selection signal and stores the corresponding symbol table. The symbol index generator stores decoding information of a plurality of encoding tables and selects a corresponding decoding information among all the decoding information according to the content selection signal. Then, the symbol index generator receives a bit stream and decodes the bit stream according to the corresponding decoding information to obtain a symbol index. After that, the symbol table buffer circuit obtains an output symbol from the corresponding symbol table according to the symbol index.

Abstract: The exemplary embodiments of the present invention are direct to a method for generating a resampling reference picture and an apparatus and video decoding system using this method. The video image decoding system is used to decode a bit stream, so as to obtain a current frame. The method for generating a resampling reference picture includes following steps: (a) looking ahead specific information of next x frames of the current frame in the bit stream; (b) determining whether to generate a resampling reference picture according to the specific information of the next x frames.

Abstract: A chip mount for a data storage device is mounted on a circuit board and has a frame and multiple legs being separately mounted through the frame and being soldered to the circuit board. A chip is mounted in a chip room of the frame and is connected to the circuit board through the legs. The chip mount prevents the chip from being damaged while being soldered to the circuit board. Furthermore, since the chip is removably mounted in the chip room of the frame of the chip mount, the chip is easily replaced with another chip to enlarge a storage capacity or renovate the data storage device. No new data storage device needs to be bought saving money and materials.

Abstract: An entropy decoding circuit, an entropy decoding method, and an entropy decoding method using a pipeline manner are provided. The entropy decoding circuit includes a coefficient register unit, a first entropy decoder, a read/write control circuit, and a second entropy decoder. The first entropy decoder reads a first stream to be decoded to perform a first entropy decoding process thereupon and writes it to the coefficient register unit in an adaptive scan order through the read/write control circuit. The second entropy decoder reads a second stream to be decoded and performs a decoding process thereupon according to a normalization parameter and whether a normalized coefficient is zero or not. Meanwhile, the normalized coefficient in the coefficient register unit is read out in a fixed scan order through the read/write control circuit to complete the decoding process.

Abstract: An entropy encoding circuit having two entropy encoders is provided. A first encoding procedure performs an adaptive scan on the encoding coefficient, and the second encoding procedure performs a fixed scan on the encoding coefficient. One of the entropy encoders receives a first encoding coefficient and performs the first encoding procedure on the first encoding coefficient to output a first encoded stream data. The other entropy encoder receives a second encoding coefficient and a normalization signal and performs the second encoding procedure on the second encoding coefficient according to the normalization signal to output a second encoded stream data. The entropy encoding circuit alternatively outputs the first encoded stream data and the second encoded stream data.

Abstract: A method and an apparatus for generating a coded block pattern for highpass coefficients are provided. The method includes receiving a quantized highpass coefficient (HP), wherein the HP includes a macroblock data; dividing the macroblock into a plurality of blocks; performing lapped transform (LT) operations of two stages on the said block data, concurrently calculating a plurality of coded block patterns of the blocks corresponding to all possible HP prediction directions; performing a calculation to obtain selection information of the HP prediction directions according to lowpass coefficients (LPs) generated through LT operations of the two stages; selecting a corresponding coded block pattern among the said coded block patterns according to the above-mentioned selection information of the HP prediction directions and outputting the selected coded block pattern.

Abstract: A hardware implementation method for concurrently realizing overlap filter and core transform and an operation method thereof are provided. The overlap filter and core transform can be adjusted according to different specifications, processes, and operation frequencies. The hardware implementation method and the operation method thereof adopt a transform-level hardware sharing architecture and multi-port input/output register array, thereby efficiently realizing overlap filter and core transform.

Abstract: An interpolation method for decimal motion estimation and a method and apparatus for calculating cost functions derived from the interpolation method are provided. The interpolation method comprises the following steps. First, divide the data range needed by an interpolation filtering process into a loaded range and a speculation range. Load the data in the loaded range and then generate the data in the speculation range based on the data in the loaded range. Finally, use the data range as input data to perform the interpolation filtering process.

Abstract: An apparatus for motion estimation which supports multiple video compression standards and the method thereof is provided. The apparatus uses an interpolation filter with fixed coefficients. The apparatus also adjusts block sizes and calculation details of cost functions according to various video compression standards. Therefore the apparatus is capable of supporting multiple standards and providing high-quality video compression.

Abstract: A method and an apparatus for cost calculation in decimal motion estimation are provided. The method comprises the following steps. Firstly, perform interpolation on a current block to get an interpolation result of a position corresponding to a decimal motion vector. Secondly, calculate a cost according to data at integer point positions of a reference frame corresponding to the current block and the decimal motion vector, and according to the interpolation result.

Abstract: A method for motion estimation and the apparatus thereof are provided. The method for motion estimation uses multi-resolution hierarchical search and allows splitting the optimal block mode at the level of the lowest resolution. The method also allows further splitting of blocks during local refinement at levels of higher resolutions.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay. And separating the computing node of said basic computing units into 2 adders then applying flipping architecture to shorten the critical path, therefore not only can keep the merits of Lifting Scheme in hardware requirement but also can shorten the critical path to achieve the optimized hardware architecture.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay.