Abstract: Systems and methods are disclosed for partitioning a cache for application of a replacement policy. For example, some methods may include partitioning entries of a set in a cache into two or more subsets; receiving a message that will cause a cache block replacement; responsive to the message, selecting a way of the cache by applying a replacement policy to entries of the cache from only a first subset of the two or more subsets; and responsive to the message, evicting an entry of the cache in the first subset and in the selected way.

Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.

Abstract: A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.

Abstract: A display panel includes a first substrate, pixel structures, a second substrate, a display medium, a first sealant, and a second sealant. The first substrate includes an active area and a peripheral area outside the active area. The pixel structures are disposed on the active area of the first substrate. The second substrate is disposed opposite to the first substrate. The first sealant is disposed between the first substrate and the second substrate, and is located on the peripheral area of the first substrate. The second sealant is disposed on a side wall of the first substrate and a side wall of the second substrate. The second sealant includes a convex surface overlapped with the side wall of the first substrate and the side wall of the second substrate.

Abstract: The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

Abstract: A control device for controlling a power generation system comprises a reception module, for receiving environmental data from the power generation system; an environment generation module, coupled to the reception module, for generating an environment state of the power generation system according to the environment data and an environment model; a strategy generation module, coupled to the environment generation module, for generating a power of the power generation system according to the environmental state, and for generating a control strategy of the power generation system according to the power; a transmission module, coupled to the strategy generation module, for transmitting the control strategy to the power generation system.

Abstract: Disclosed herein is a carbon nanodot-polyacrylic acid composite hydrogel including a polyacrylic acid-based gel matrix having carboxyl groups, and a plurality of fluorescent carbon nanodots having amino groups on surfaces thereof. The fluorescent carbon nanodots are formed by subjecting polyethylenimine and hydrochloric acid to a hydrothermal reaction, and are distributed in the polyacrylic acid-based gel matrix. The amino groups of the fluorescent carbon nanodots are covalently bonded with the carboxyl groups of the polyacrylic acid-based gel matrix. Also disclosed herein are a method for preparing and a formulation for forming a carbon nanodot-polyacrylic acid composite hydrogel.

Abstract: A display device includes a display panel, first and second conductive pads, a conductive adhesive layer and a circuit board. First and second leads are on a first substrate of the display panel and extended to be exposed at a side. A patterned electrode layer is on a second substrate of the display panel and partially exposed at the side. A spacer layer is on the first substrate and covers the first and second leads. A thickness of the spacer layer on the first lead is smaller than a thickness of the remaining part of the spacer layer. The first and second conductive pads are at the side of the display panel. The first conductive pads are extended to a space between the patterned electrode layer and the spacer layer on the first leads. The second conductive pads are connected to the second leads and the spacer layer thereon.

Abstract: A processor circuit is provided. The processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a load instruction to generate a decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instruction is in a load-use scenario. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the load instruction according to the decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instruction is in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.

Abstract: A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.

Abstract: A display device includes a display panel, first and second conductive pads, a conductive adhesive layer and a circuit board. First and second leads are on a first substrate of the display panel and extended to be exposed at a side. A patterned electrode layer is on a second substrate of the display panel and partially exposed at the side. A spacer layer is on the first substrate and covers the first and second leads. A thickness of the spacer layer on the first lead is smaller than a thickness of the remaining part of the spacer layer. The first and second conductive pads are at the side of the display panel. The first conductive pads are extended to a space between the patterned electrode layer and the spacer layer on the first leads. The second conductive pads are connected to the second leads and the spacer layer thereon.

Abstract: A display panel includes a first substrate, pixel structures, a second substrate, a display medium, a first sealant, and a second sealant. The first substrate includes an active area and a peripheral area outside the active area. The pixel structures are disposed on the active area of the first substrate. The second substrate is disposed opposite to the first substrate. The first sealant is disposed between the first substrate and the second substrate, and is located on the peripheral area of the first substrate. The second sealant is disposed on a side wall of the first substrate and a side wall of the second substrate. The second sealant includes a convex surface overlapped with the side wall of the first substrate and the side wall of the second substrate.

Abstract: A processor circuit is provided. The processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a load instruction to generate a decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instruction is in a load-use scenario. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the load instruction according to the decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instruction is in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.

Abstract: The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

Abstract: A data write system includes a main memory, a cache memory, and a core processing circuit. The main memory includes a restricted region and a non-restricted region. The cache memory is coupled to the main memory. The cache memory includes multiple ways. The core processing circuit is coupled to the cache memory and includes a logic circuit. The logic circuit is configured to select one of the ways as a selected way according to an access address of the main memory, the restricted region, and mode setting information, to write data corresponding to the access address into the selected way.

Abstract: A compound, a method of synthesizing a compound with pyridine ring, and a light-emitting element are provided. The compound has a structure represented by formula (1), wherein ring A and ring B represent the same or different substituted or unsubstituted pyridine rings, respectively; A1 and A2 represent the same or different organic groups, respectively; R1 and R2 represent the same or different substituents, respectively; m and n represent 0, 1, 2 or 3, respectively.

Abstract: A regenerative displacer for use in a stirling engine includes two opposite covers with respective through openings, a body engaging the covers to define an accommodation space therein, a regenerator disposed in the accommodation space, and a rod inserted through the regenerator and one of the covers into a cooling portion of the stirling engine. The regenerator has a plurality of channels. Each channel has two open ends and a heat collecting net engaging each open end. Working gas passing through the regenerative displacer can be concentrated at the open ends and can absorb and release heat quickly because of the heat collecting nets, thereby increasing the efficiency of heat exchange and a temperature difference of the working gas in a thermodynamic cycle. Accordingly, pressure is increased to facilitate a quick reciprocation of a power piston of the stirling engine, and this increases output power and saves energy.

Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.

Abstract: A method for managing traffic item in software defined networking includes establishing a downlink flow table of a switch according to the flow entries, establishing an uplink flow table of the switch according to the flow entries, acquiring a data packet by the switch, and generating a transmission path to allocate the data packet according to the data packet, the downlink flow table, and the uplink flow table. The downlink flow table includes a correlation between first transmission ports of the switch and down link switches. The uplink flow table includes a correlation between the first transmission ports and a transmission port group of uplink switches.

Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.