Abstract: A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.

Abstract: A method, system and external instrument are provided. The method initiates a communication link between an external instrument (EI) and an implantable medical device (IMD), established a first connection interval for conveying data packets between the EI and IMD and monitors a connection criteria that includes at least one of a data throughput requirement. A battery indicator or link condition of the communications link is between the IMD and EI. The method further changes from the first connection interval to a second connection interval based on the connection criteria.

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

Abstract: A package structure includes a first die, a die stack structure, a support structure and an insulation structure. The die stack structure is bonded to the first die. The support structure is disposed on the die stack structure. A width of the support structure is larger than a width of the die stack structure and less than a width of the first die. The insulation structure at least laterally wraps around the die stack structure and the support structure.

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.

Abstract: In one example, an adapter card may include a circuit board having a male interface to be inserted into a discrete graphics card slot and a peripheral component interconnect express (PCIe) slot to communicatively couple a PCIe device. Further, the adapter card may include a voltage converter circuit disposed on the circuit board to convert a first voltage associated with the discrete graphics card slot to a second voltage corresponding to the PCIe device and a level shifter circuit disposed on the circuit board to modify a signal level in the discrete graphics card slot to a signal level in the PCIe device.

Abstract: A microelectronic device comprises a die comprising a front side and a back side opposite the front side, one or more components of integrated circuitry within a base material of the die and between the front side and the back side of the die, and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors comprise a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further comprises a first conductive via comprising a conductive material extending through the base material, the first conductive via in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device. Related apparatuses including a decoupling capacitor in a back side, and related electronic systems and methods are also described.

Abstract: Examples described herein relate to a non-transitory machine-readable medium consistent with the disclosure. For instance, the non-transitory machine-readable medium may store instruction executable by a processing resource to transfer additional power through a power delivery cable, input the additional power to a component of a computing device, and sequence the additional power with a main power supply of the computing device.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.

Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.

Abstract: A power supply device (20, 20?, 20?) and a printed circuit board device (100, 100?, 100?) including the same are provided in embodiments of the present disclosure. The power supply device (20, 20?, 20?) is mounted on a mainboard (10) and includes a first surface (11). The power supply device (20, 20?, 20?) includes: a magnetic device (22) located above the first surface (11) of the mainboard (10) and electrically connected to the mainboard (10); at least one accommodating portion (24) located on a surface of the magnetic device (22) facing towards the first surface (11); and a semiconductor device (26) which is at least partially accommodated in the at least one accommodating portion (24) and electrically connected to the mainboard (10).

Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.

Abstract: A wireless communication terminal including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from an AP. The controller is coupled to the wireless transceiver, and is operable to configure the wireless communication terminal to operate as a non-AP STA, and transmit a MU PPDU with a single RU spanning a partial bandwidth of the MU PPDU to the AP via the wireless transceiver. In particular, the partial bandwidth excludes a frequency band of a primary channel.

Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

Abstract: A semiconductor package includes a first die, a plurality of second dies and a through via. The second dies are disposed over and electrically connected to the first die. The through via is disposed between the second dies and electrically connected to the first die. The through via includes a first portion having a first width and a second portion having a second width different from the first width and disposed between the first portion and the first die. The first portion includes a first seed layer and a first conductive layer, and the first seed layer is disposed aside an interface between the first portion and the second portion.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.