Patents by Inventor Chao-Wen (Kevin) Chen

Chao-Wen (Kevin) Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164848
    Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Sung-Feng Yeh, Tzuan-Horng Liu, Chuan-An Cheng
  • Publication number: 20210327807
    Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210321527
    Abstract: A power supply device (20, 20?, 20?) and a printed circuit board device (100, 100?, 100?) including the same are provided in embodiments of the present disclosure. The power supply device (20, 20?, 20?) is mounted on a mainboard (10) and includes a first surface (11). The power supply device (20, 20?, 20?) includes: a magnetic device (22) located above the first surface (11) of the mainboard (10) and electrically connected to the mainboard (10); at least one accommodating portion (24) located on a surface of the magnetic device (22) facing towards the first surface (11); and a semiconductor device (26) which is at least partially accommodated in the at least one accommodating portion (24) and electrically connected to the mainboard (10).
    Type: Application
    Filed: May 18, 2018
    Publication date: October 14, 2021
    Inventors: Tai MA, Chao WEN
  • Publication number: 20210314951
    Abstract: A wireless communication terminal including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from an AP. The controller is coupled to the wireless transceiver, and is operable to configure the wireless communication terminal to operate as a non-AP STA, and transmit a MU PPDU with a single RU spanning a partial bandwidth of the MU PPDU to the AP via the wireless transceiver. In particular, the partial bandwidth excludes a frequency band of a primary channel.
    Type: Application
    Filed: March 18, 2021
    Publication date: October 7, 2021
    Inventors: Cheng-Yi CHANG, Chao-Wen CHOU, Kun-Sheng HUANG, Fu-Yu TSAI, Hung-Tao HSIEH
  • Publication number: 20210315031
    Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 7, 2021
    Inventors: Yongjian Wu, Jyoti Bhayana, Chao-Wen Young, Tejpal Singh, Samir Shah
  • Publication number: 20210313671
    Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Publication number: 20210305094
    Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 30, 2021
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210305214
    Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Hsien-Wei Chen, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20210296288
    Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210296289
    Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Kyle K. Kirby, Chao Wen Wang
  • Publication number: 20210296251
    Abstract: A semiconductor package includes a first die, a plurality of second dies and a through via. The second dies are disposed over and electrically connected to the first die. The through via is disposed between the second dies and electrically connected to the first die. The through via includes a first portion having a first width and a second portion having a second width different from the first width and disposed between the first portion and the first die. The first portion includes a first seed layer and a first conductive layer, and the first seed layer is disposed aside an interface between the first portion and the second portion.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210288030
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Publication number: 20210281063
    Abstract: An over current isolation circuit may, in an example, include a control chip, an input/output embedded controller communicatively coupled to the control chip, and an isolation circuit to isolate the control chip from an over current event based on a user selected preference to selectively enable and disable the signal of the over current event to the control chip.
    Type: Application
    Filed: October 19, 2017
    Publication date: September 9, 2021
    Inventors: Poying Chih, Chao-Wen Cheng, Shu Ming Kuo
  • Patent number: 11114413
    Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210265289
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping CHIANG, Yi-Che CHIANG, Nien-Fang WU, Min-Chien HSIAO, Chao-Wen SHIH, Shou-Zen CHANG, Chung-Shi LIU, Chen-Hua YU
  • Publication number: 20210257717
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 19, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 11094862
    Abstract: A bonding method of a semiconductor device is disclosed. The method includes steps of forming a plurality of holes on two bonding parts of a main substrate, respectively; disposing a semiconductor device on the main substrate, and aligning the two bonding parts with two conduction parts of the semiconductor device; aligning a laser to the conduction parts and operating the laser to emit a laser beam from a lower part of the main substrate, wherein the laser beam passes through the holes of the bonding part to strike on the conduction part, so as to melt each conduction part to bond with the bonding part. With configuration of the holes, the conduction parts and the bonding part can be smoothly bonded by using laser, so as to achieve the purpose of transferring the semiconductor device.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 17, 2021
    Assignee: PRILIT OPTRONICS, INC.
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Hsing-Ying Lee
  • Publication number: 20210249380
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210242276
    Abstract: A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • FAN
    Publication number: 20210231127
    Abstract: A fan includes a motor base, a bearing, an impeller, a stator and a magnetic element. The motor base has a bearing stand in a center portion thereof. The impeller includes a metallic case, plural blades and a rotating shaft. A top surface of a top wall of the metallic case continuous with curved surface that defines part of a central opening, and a depth of the central opening is equal to a thickness of the top wall. The blades are disposed around an outer periphery of said metallic case. The rotating shaft is inserted into the central opening and penetrated through the bearing stand, wherein no raised ring structure is formed in the top wall, and the rotating shaft and the metallic case are jointed together by a laser welding process. The magnetic element is disposed on an inner wall of the metallic case and aligned with the stator.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Chiu-Kung Chen, Chao-Wen Lu