Patents by Inventor Chao-Wen Lay

Chao-Wen Lay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050275046
    Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned.
    Type: Application
    Filed: June 14, 2004
    Publication date: December 15, 2005
    Inventors: Matthias Goldbach, Frank Jakubowski, Ralf Koepe, Chao-Wen Lay, Kristin Schupke, Michael Schmidt, Cheng-Chih Huang
  • Patent number: 6759300
    Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: July 6, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Chao-Wen Lay, Yu-Chi Sun, Tse-Yao Huang
  • Publication number: 20040110342
    Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.
    Type: Application
    Filed: April 28, 2003
    Publication date: June 10, 2004
    Applicant: Nanya Technology Corporation
    Inventors: Chao-Wen Lay, Yu-Chi Sun, Tse-Yao Huang