Patents by Inventor Charalampos Pozidis

Charalampos Pozidis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230108194
    Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.
    Type: Application
    Filed: October 6, 2021
    Publication date: April 6, 2023
    Inventors: Nikolaos Papandreou, ROMAN ALEXANDER PLETKA, Radu Ioan Stoica, Nikolas Ioannou, Charalampos Pozidis, Timothy J. Fisher, Aaron Daniel Fry
  • Publication number: 20230057271
    Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.
    Type: Application
    Filed: August 18, 2021
    Publication date: February 23, 2023
    Inventors: RADU IOAN STOICA, NIKOLAS IOANNOU, ROMAN ALEXANDER PLETKA, NIKOLAOS PAPANDREOU, CHARALAMPOS POZIDIS
  • Patent number: 11567673
    Abstract: A data storage system includes a plurality of storage devices organized as a redundant array of inexpensive disks (RAID) storage array and a RAID controller. The RAID controller monitors the plurality of storage devices in the RAID storage array. The RAID controller also detects that a host read request of a host has a latency exceeding a latency threshold. Based on the monitoring, the RAID controller determines whether a proactive rebuild of a data requested by the host read request in absence of a data error would likely be beneficial to performance. Based on determining that a proactive rebuild of the data requested by the host read request would likely be beneficial to performance, the RAID controller initiates the proactive rebuild of the data and sends the requested data to the host.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Radu Ioan Stoica, Nikolas Ioannou, Roman Alexander Pletka, Nikolaos Papandreou, Charalampos Pozidis
  • Publication number: 20230016368
    Abstract: A method is provided for accelerating machine learning inferences. The method uses an ensemble model run on input data. This ensemble model involves several base learners, where each of the base learners has been trained. The method first schedules tasks for execution. As a result of the task scheduling, one of the base learners is executed based on a subset of the input data. The execution of the tasks is then started to obtain respective task outcomes. An exit condition is repeatedly evaluated while executing the tasks by computing a deterministic function of the task outcomes obtained so far. This deterministic function output values indicate whether an inference result of the ensemble model has converged. Accordingly, the execution of the tasks can be interrupted if the exit condition evaluated last is found to be fulfilled. Eventually, an inference result of the ensemble model is estimated based on the task outcomes.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Inventors: Jan Van Lunteren, Charalampos Pozidis
  • Publication number: 20230010632
    Abstract: A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 12, 2023
    Inventors: ROMAN ALEXANDER PLETKA, AARON DANIEL FRY, NIKOLAOS PAPANDREOU, RADU IOAN STOICA, CHARALAMPOS POZIDIS, NIKOLAS IOANNOU
  • Publication number: 20220415424
    Abstract: A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Nikolaos Papandreou, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Charalampos Pozidis, Timothy J. Fisher, Andrew D. Walls
  • Publication number: 20220413762
    Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: ROMAN ALEXANDER PLETKA, TIMOTHY J. FISHER, ADALBERTO GUILLERMO YANES, NIKOLAOS PAPANDREOU, RADU IOAN STOICA, CHARALAMPOS POZIDIS, NIKOLAS IOANNOU
  • Publication number: 20220398015
    Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 15, 2022
    Inventors: Jan Van Lunteren, Charalampos Pozidis
  • Publication number: 20220358356
    Abstract: A computer-implemented method forecasts a timeseries. The method includes loading and running a machine learning model. The machine learning model includes an encoder recurrent neural network (RNN) mapping an input sequence into a fixed-dimensionality vector c and a decoder RNN decoding the vector to produce an intermediate sequence. The model includes a fully connected feed-forward layer (FC-FFL) to produce an output sequence. The machine learning model is run concomitantly. Values of a given input sequence are coupled to produce a given output sequence in output of the FC-FFL. Values of a feedback sequence are stored in a location-addressable memory bank. The memory addresses of the memory bank are mapped onto a temporal sequence of the feedback sequence. Values stored are read to retrieve values of the feedback sequence. The retrieved values are fed to the decoder RNN as the model is being run to obtain the given output sequence.
    Type: Application
    Filed: April 21, 2021
    Publication date: November 10, 2022
    Inventors: Mircea R. Gusat, Konstantinos Kouziou, Charalampos Pozidis
  • Patent number: 11474920
    Abstract: Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Charalampos Pozidis, Thomas Mittelholzer, Nikolaos Papandreou, Milos Stanisavljevic
  • Patent number: 11461694
    Abstract: Methods are provided for implementing training of a machine learning model in a processing system, together with systems for performing such methods. A method includes providing a core module for effecting a generic optimization process in the processing system, and in response to a selective input, defining a set of derivative modules, for effecting computation of first and second derivatives of selected functions ƒ and g in the processing system, to be used with the core module in the training operation. The method further comprises performing, in the processing system, the generic optimization process effected by the core module using derivative computations effected by the derivative modules.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Thomas Parnell, Celestine Duenner, Dimitrios Sarigiannis, Charalampos Pozidis
  • Publication number: 20220198281
    Abstract: An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventors: Jan Van Lunteren, Nikolas Ioannou, Nikolaos Papandreou, Thomas Parnell, Andreea Anghel, Charalampos Pozidis
  • Patent number: 11360903
    Abstract: A computer-implemented method, according to one approach, includes: determining a current read heat value of each logical page which corresponds to write requests that have accumulated in a destage buffer. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Other systems, methods, and computer program products are described in additional approaches.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20220179766
    Abstract: A computer-implemented method, computer program product and computer system of characterizing a computerized system, where data can be written to or read from the system via write channels and read channels. Including accessing first data, pertaining to the write channels, and second data, pertaining to the read channels and may continually collect, aggregate, and access data. The first data and the second data are separately fed into a convolutional or recurrent neural network, which includes two input channels defining independent subsets of one or more layers and an output layer connected by each subsets of layers. Data ingestion is performed for the neural network to separately process the first data and the second data and produce one or more values in the output layer. A current state can be characterized based on the values produced. A potential anomaly is detected in the system, and action may be taken.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Mircea R. Gusat, Charalampos Pozidis, Athanasios Fitsios
  • Publication number: 20220180179
    Abstract: A computer-implemented method for detecting an anomaly in a computer system. The method comprises accessing a first timeseries of measured values of a quantity related to the operation of the computer system, wherein the first timeseries spans a first time period. Timeseries forecasting is performed to infer a second timeseries of values for the quantity. The second timeseries spans a second time period up to a given time horizon. Aa third timeseries of measured values of the quantity is accessed, wherein the third timeseries spans the second time period up to the time horizon. The second timeseries inferred is subsequently compared with the third timeseries accessed to obtain a comparison outcome. An anomaly score is determined based on the comparison outcome obtained, to potentially detect an anomaly in the computer system. The invention is further directed to an anomaly detection unit and a computer program product.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Mircea R. Gusat, Athanasios Fitsios, Charalampos Pozidis, Konstantinos Kouziou
  • Publication number: 20220180211
    Abstract: According to one embodiment, a method, computer system, and computer program product for training a cognitive model that involves one or more decision trees as base learners is provided. The present invention may include constructing, by a tree building algorithm, the one or more decision trees, wherein the constructing further comprises associating one or more training examples with one or more leaf nodes of the one or more decision trees and iteratively running a breadth-first search tree builder on one or more of the decision trees to perform one or more tree building operations; and training the cognitive model based on the one or more decision trees.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 9, 2022
    Inventors: Nikolas Ioannou, Thomas Parnell, Andreea Anghel, Nikolaos Papandreou, Charalampos Pozidis
  • Patent number: 11334492
    Abstract: A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 17, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Roman Alexander Pletka, Sasa Tomic, Nikolas Ioannou, Radu Ioan Stoica
  • Patent number: 11315035
    Abstract: Computer-implemented methods are provided for implementing training of a machine learning model in a heterogeneous processing system comprising a host computer operatively interconnected with an accelerator unit. The training includes a stochastic optimization process for optimizing a function of a training data matrix X, having data elements Xi,j with row coordinates i=1 to n and column coordinates j=1 to m, and a model vector w having elements wj. For successive batches of the training data, defined by respective subsets of one of the row coordinates and column coordinates, random numbers associated with respective coordinates in a current batch b are generated in the host computer and sent to the accelerator unit. In parallel with generating the random numbers for batch b, batch b is copied from the host computer to the accelerator unit.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Parnell, Celestine Duenner, Charalampos Pozidis, Dimitrios Sarigiannis
  • Patent number: 11302403
    Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
  • Patent number: 11301776
    Abstract: A method for a machine learning model training is provided which operates in a mixed CPU/GPU environment. The amount of general processing unit memory is larger than the amount of special processing unit memory. The method includes loading a complete training data set into the memory of the general processing unit, determining importance values relating to training data vectors in the provided training data set of the training data vectors, dynamically transferring training data vectors of the training data set from the general processing unit memory to a special processing unit memory using as decision criteria the importance value of the training data vector, wherein the importance value used is taken from an earlier training round of the machine learning model, and executing a training algorithm on the special processing unit with the training data vectors having the highest available importance values of one of the earlier training rounds.
    Type: Grant
    Filed: April 14, 2018
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Celestine Duenner, Thomas P. Parnell, Charalampos Pozidis