Patents by Inventor Charan K. Gurumurthy

Charan K. Gurumurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9966351
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20170202080
    Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 13, 2017
    Inventors: Ching-Ping Janet Shen, Ravi Shankar, Yonggang Li, Dilan Seneviratne, Charan K. Gurumurthy
  • Patent number: 9698114
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: July 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Patent number: 9554472
    Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Ching-Ping Janet Shen, Ravi Shankar, Yonggang Li, Dilan Seneviratne, Charan K. Gurumurthy
  • Patent number: 9554468
    Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a base, situating an adhesive layer on the inner foil, such that the inner foil is substantially flush with a periphery of the base, situating an outer conductive foil on the adhesive layer, or covering an interface between the adhesive layer, the inner foil and the outer conductive foil with a protective material.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Ching-Ping Janet Shen, Charan K. Gurumurthy, Dilan Seneviratne, Ravi Shankar, Liwen Jin, Deepak Arora
  • Publication number: 20160365325
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9449936
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20150181717
    Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.
    Type: Application
    Filed: March 27, 2014
    Publication date: June 25, 2015
    Inventors: Ching-Ping Janet Shen, Ravi Shankar, Yonggang Li, Dilan Seneviratne, Charan K. Gurumurthy
  • Publication number: 20150179600
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Publication number: 20150181713
    Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a base, situating an adhesive layer on the inner foil, such that the inner foil is substantially flush with a periphery of the base, situating an outer conductive foil on the adhesive layer, or covering an interface between the adhesive layer, the inner foil and the outer conductive foil with a protective material.
    Type: Application
    Filed: March 27, 2014
    Publication date: June 25, 2015
    Inventors: Ching-Ping Janet Shen, Charan K. Gurumurthy, Dilan Seneviratne, Ravi Shankar, Liwen Jin, Deepak Arora
  • Patent number: 8456016
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Publication number: 20110169167
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Patent number: 7915060
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Publication number: 20100289154
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Application
    Filed: March 23, 2010
    Publication date: November 18, 2010
    Inventors: Yonggang Li, Amruthavalll P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Patent number: 7749900
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Publication number: 20100148365
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Publication number: 20100078805
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Patent number: 7670951
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Publication number: 20090250824
    Abstract: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Inventors: Xiwang Qi, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy, Isao Yamada
  • Publication number: 20080251932
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 16, 2008
    Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy