Patents by Inventor Charan K. Gurumurthy
Charan K. Gurumurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9966351Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: August 24, 2016Date of Patent: May 8, 2018Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20170202080Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.Type: ApplicationFiled: January 23, 2017Publication date: July 13, 2017Inventors: Ching-Ping Janet Shen, Ravi Shankar, Yonggang Li, Dilan Seneviratne, Charan K. Gurumurthy
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Patent number: 9698114Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: March 25, 2011Date of Patent: July 4, 2017Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Patent number: 9554472Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.Type: GrantFiled: March 27, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Ching-Ping Janet Shen, Ravi Shankar, Yonggang Li, Dilan Seneviratne, Charan K. Gurumurthy
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Patent number: 9554468Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a base, situating an adhesive layer on the inner foil, such that the inner foil is substantially flush with a periphery of the base, situating an outer conductive foil on the adhesive layer, or covering an interface between the adhesive layer, the inner foil and the outer conductive foil with a protective material.Type: GrantFiled: March 27, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Ching-Ping Janet Shen, Charan K. Gurumurthy, Dilan Seneviratne, Ravi Shankar, Liwen Jin, Deepak Arora
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Publication number: 20160365325Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Patent number: 9449936Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: March 6, 2015Date of Patent: September 20, 2016Assignee: INTEL CORPORATIONInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20150181717Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a substantially rectangular base, situating an outer conductive foil situated on the inner foil, or coupling, using a connective material, the inner foil and the outer conductive foil near edges of the outer conductive foil and the inner foil.Type: ApplicationFiled: March 27, 2014Publication date: June 25, 2015Inventors: Ching-Ping Janet Shen, Ravi Shankar, Yonggang Li, Dilan Seneviratne, Charan K. Gurumurthy
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Publication number: 20150179600Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: March 6, 2015Publication date: June 25, 2015Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
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Publication number: 20150181713Abstract: Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a releasable core panel can include coupling an inner foil to a base, situating an adhesive layer on the inner foil, such that the inner foil is substantially flush with a periphery of the base, situating an outer conductive foil on the adhesive layer, or covering an interface between the adhesive layer, the inner foil and the outer conductive foil with a protective material.Type: ApplicationFiled: March 27, 2014Publication date: June 25, 2015Inventors: Ching-Ping Janet Shen, Charan K. Gurumurthy, Dilan Seneviratne, Ravi Shankar, Liwen Jin, Deepak Arora
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Patent number: 8456016Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: GrantFiled: March 23, 2010Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Publication number: 20110169167Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: March 25, 2011Publication date: July 14, 2011Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Patent number: 7915060Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: February 26, 2010Date of Patent: March 29, 2011Assignee: Intel CorporationInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Publication number: 20100289154Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: ApplicationFiled: March 23, 2010Publication date: November 18, 2010Inventors: Yonggang Li, Amruthavalll P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Patent number: 7749900Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: GrantFiled: September 30, 2008Date of Patent: July 6, 2010Assignee: Intel CorporationInventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Publication number: 20100148365Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: ApplicationFiled: February 26, 2010Publication date: June 17, 2010Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Publication number: 20100078805Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Patent number: 7670951Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.Type: GrantFiled: June 27, 2005Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
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Publication number: 20090250824Abstract: A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder.Type: ApplicationFiled: April 4, 2008Publication date: October 8, 2009Inventors: Xiwang Qi, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy, Isao Yamada
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Publication number: 20080251932Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.Type: ApplicationFiled: June 12, 2008Publication date: October 16, 2008Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy