Patents by Inventor Charan K. Gurumurthy

Charan K. Gurumurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming through-silicon vias with stress buffer collars and resulting devices
    Patent number: 7402515
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy
  • Integrated circuit package with low modulus layer and capacitor/interposer
    Patent number: 7042077
    Abstract: A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Michael J. Walk, Hamid Azimi, John S. Guzek, Charan K. Gurumurthy
  • Method of forming an integrated circuit substrate
    Patent number: 6858475
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • METHOD OF FORMING AN INTEGRATED CIRCUIT SUBSTRATE
    Publication number: 20040266070
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin