Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Techniques are disclosed for dynamic random access memory (DRAM) cell. The DRAM cell comprises a first bit line and a first complementary bit line, a storage capacitor having a first node coupled with the first complementary bit line, and a transistor selectable by a word line to couple a second node of the storage capacitor to the first bit line, wherein a voltage potential across the first bit line and the first complementary bit line when the transistor is selected is indicative of a bit of data.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: An aspect includes identifying a repaired memory array element in a memory array, and identifying memory array elements in the memory array that are adjacent to the repaired memory array element. A group that includes the repaired and adjacent memory array elements is formed and monitored for error conditions. It is determined whether a number of the error conditions exceeds a threshold. A repair action is performed to the memory array based on determining that the number of error conditions exceeds the threshold.

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

Abstract: An aspect includes identifying a repaired memory array element in a memory array, and identifying memory array elements in the memory array that are adjacent to the repaired memory array element. A group that includes the repaired and adjacent memory array elements is formed and monitored for error conditions. It is determined whether a number of the error conditions exceeds a threshold. A repair action is performed to the memory array based on determining that the number of error conditions exceeds the threshold.

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.