Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

Abstract: A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.

Abstract: A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

Abstract: A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.

Abstract: A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently of the second port. The memory module further includes a first memory device bus in communication with the first port and the first group of memory devices, and a second memory device bus in communication with the second port and the second group of memory devices. The memory module further includes a hub device configured to re-drive information in a cascade interconnect system. The hub device includes logic for reading data from and writing data to the ranks of memory devices via the first and second ports and the first and second memory device buses.

Abstract: A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.

Abstract: A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices.

Abstract: A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.

Abstract: A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of memory cells. A refresh address counter indicates the address of the row of cells for refreshing. A temporary data storer is used for storing data from the memory cell indicated for refreshing. A data inverter inverts data from the memory cell indicated for refreshing. A comparator associated with the temporary data storer and the data inverter compares data in those devices. An indicator bit is associated with the refresh address counter to indicate whether the data stored in the address indicated by the refresh address counter is inverted.

Abstract: A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of memory cells. A refresh address counter indicates the address of the row of cells for refreshing. A temporary data storer is used for storing data from the memory cell indicated for refreshing. A data inverter inverts data from the memory cell indicated for refreshing. A comparator associated with the temporary data storer and the data inverter compares data in those devices. An indicator bit is associated with the refresh address counter to indicate whether the data stored in the address indicated by the refresh address counter is inverted.