Abstract: A compound of Formula I, is provided. In Formula I, one of Z1, Z2, and Z3 is N and the remainder are C; each of L1 and L2 is independently selected from a direct bond and a linking group; at least one of R1, R2, RA, RB, RC, RD, and RE comprises a group R* having a structure selected form the group consisting of Formula II, -Q(R3)(R4)a(R5)b, Formula III, and Formula IV, Each R, R?, R?, R1, R2, R3, R4, R5, RA, RB, RC, RD, RE, RF, RG, and RH is independently hydrogen or a General Substituent, with the proviso that group R* is not adamantyl. Formulations, OLEDs, and consumer products containing the compound are also provided.

Abstract: An electrical connector includes a fastening part, a connector body assembled under the fastening part and defining at least one receiving groove at a mating end thereof, a base board positioned under the connector body, and a shielding shell. The connector body and the base board can be firmly fastened in the shielding shell by means of the fastening part. At least one end edge of the shielding shell is bent inward to form a positioning tail positioned in the receiving groove to position the mating end of the connector body with a front face of the mating end being flush with the end edge of the shielding shell and a contact face of the connector body being substantially flush with a top edge of the positioning tail, so as to avoid the mating end of the connector body wrapping in use.

Abstract: An electrical connector includes a base board having a plurality of first contact pads and second contact pads exposed on one end of the base board, a plurality of first terminals each having one end thereof connected with the corresponding first contact pad of the base board, a plurality of second terminals each having one end thereof arranged alternately with the first terminals and connected with the corresponding second contact pad of the base board, and an insulating housing having a window. The other end of the first terminal is slanted downward at an angle and then curved upward back to form a barb-like contact portion. The other end of the second terminal defines a contact protrusion. The base board together with the first terminals and the second terminals are disposed in the insulating housing. The contact portions and the contact protrusions are exposed outside through the window.

Abstract: An electrical connector includes a fastening part, a connector body assembled under the fastening part and defining at least one receiving groove at a mating end thereof, a base board positioned under the connector body, and a shielding shell. The connector body and the base board can be firmly fastened in the shielding shell by means of the fastening part. At least one end edge of the shielding shell is bent inward to form a positioning tail positioned in the receiving groove to position the mating end of the connector body with a front face of the mating end being flush with the end edge of the shielding shell and a contact face of the connector body being substantially flush with a top edge of the positioning tail, so as to avoid the mating end of the connector body wrapping in use.

Abstract: An electrical connector includes a base board having a plurality of first contact pads and second contact pads exposed on one end of the base board, a plurality of first terminals each having one end thereof connected with the corresponding first contact pad of the base board, a plurality of second terminals each having one end thereof arranged alternately with the first terminals and connected with the corresponding second contact pad of the base board, and an insulating housing having a window. The other end of the first terminal is slanted downward at an angle and then curved upward back to form a barb-like contact portion. The other end of the second terminal defines a contact protrusion. The base board together with the first terminals and the second terminals are disposed in the insulating housing. The contact portions and the contact protrusions are exposed outside through the window.

Abstract: The present invention relates to a USB connector, which comprises: a connector main body having its front being downwardly extended thereby forming a stop part having a first lead angle; and a substrate having plural first contact pads and plural second contact pads, so as to form a USB connector. Said USB connector allows a USB2.0 connector and a USB3.0 connector to be respectively inserted.

Abstract: The present invention relates to a USB connector, which comprises: a connector main body having its front being downwardly extended thereby forming a stop part having a first lead angle; and a substrate having plural first contact pads and plural second contact pads, so as to form a USB connector. Said USB connector allows a USB2.0 connector and a USB3.0 connector to be respectively inserted.

Abstract: A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.

Abstract: A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices.

Abstract: A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.

Abstract: Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.

Abstract: A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

Abstract: An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.

Abstract: A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Abstract: A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

Abstract: A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.

Abstract: A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N?1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.

Abstract: A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.

Abstract: Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.

Abstract: A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data.