Abstract: An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.

Abstract: A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time depends on the write data state and is relatively long for set, but short for clear. A PCM chip has a lookup table (LUT) caching write data that is later written to a PCM bank. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the slower PCM. The PCM chip has upstream and downstream serial interfaces to other PCM chips arranged as a token stub. Requests are passed down the token-stub while acknowledgements are passed up the token-stub to the host's memory controller. Shared chip-enable lines are driven by the upstream PCM chip for requests, and by the downstream PCM chip for acknowledgements.

Abstract: A system for providing security to a portable storage device coupleable to a host system and associated methods are disclosed. The system includes a portable storage device random number generator operable to generate a random number for storage in the portable storage device and the host system each time the portable storage device is accessed by the host system. A random number generated in this manner may be used by the host system in a write process to encrypt a logical branch address, a user password, and user data which may be written to the portable storage device as encrypted data and stored in a secure area of the portable storage device. The write process may further include encrypting the random number using a key associated with the portable storage device to generate an encrypted random number, which may be written to the portable storage device and associated with the encrypted data. The random number is not stored in the host system.

Abstract: A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.

Abstract: Systems, methods and apparatus related to a motorized platform for use in creating three dimensional images. The motorized platform includes a symmetrical steering system such that a digital camera remains focused upon a desired image target as the motorized platform is advanced. The symmetrical steering system includes a three-wheel arrangement providing a constant radius path around the image target. A pair of steerable wheels located on an inside edge of the motorized platform are operably connected with a steering linkage assembly such that the steerable wheels are angularly adjusted to define the constant radius path. A drive wheel is operably connected to a motor assembly for propelling the motorized platform along the constant radius path. A digital camera can be mounted to a tripod attached to the motorized platform and the digital camera can be operably controlled either manually or automatically as the motorized platform is advanced.

Abstract: A flash-memory cache card caches data that a host writes to a hard disk drive. A flash-memory array has physical blocks of flash memory arranged into first and second data areas having M blocks each, and a wear-leveling-counter pool. An incoming logical sector address (LSA) from a host is mapped to one of M entries in a RAM lookup table using a hash of modulo M. The RAM entry stores a mapping to a physical block in a foreground area that is either the first or the second data area. Pages in the physical block are read for a matching LSA that indicates a cache hit. Full pages are written back to the hard disk and erased in the background while the other data area becomes the foreground area. A new physical block with a low wear-level count is selected from blocks in the new foreground area.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.

Abstract: A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Dual-axis case-grounding pins draw any electro-static-discharges (ESD) current off the upper case along a primary axis and onto a PCBA ground through a secondary axis washer that is screwed into the PCBA. The primary axis body of the dual-axis case-grounding pins fits around a PCBA notch while the secondary axis passes through a metalized alignment hole for grounding. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the dual-axis case-grounding pins.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Abstract: A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N?1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.

Abstract: A Universal-Serial-Bus (USB) device has a USB plug with reduced wobble. A USB metal wrap around the perimeter of the USB plug is attached to a housing by overmolding. A plug supporter is inserted into the front of the USB metal wrap, and has locking tabs that snap over the inside wall of the housing. Side tabs on the plug supporter fit into side slots on the USB metal wrap to secure the plug supporter inside the USB metal wrap. A circuit board with a USB flash controller has USB metal contacts on an extension end that is inserted through the housing and into the USB metal wrap. The extension end fits underneath top tabs on the plug supporter, preventing the extension end with the USB metal contacts from upward wobble when the USB plug is inserted into a USB socket.

Abstract: A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

Abstract: A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Abstract: A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.