Abstract: Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a substrate, a waveguide disposed above the substrate, a phase change layer disposed above the waveguide, and a heater disposed above the phase change layer. The waveguide has a modifiable refractive index based at least in part on a state of a phase change material included in the phase change layer. The phase change material of the phase change layer is in a first state of a set of states, and the waveguide has a first refractive index determined based on the first state of the phase change material. The heater is to generate heat to transform the phase change material to a second state of the set of states, and the waveguide has a second refractive index determined based on the second state of the phase change material. Other embodiments may also be described and claimed.

Abstract: Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a substrate, a waveguide disposed above the substrate, a phase change layer disposed above the waveguide, and a heater disposed above the phase change layer. The waveguide has a modifiable refractive index based at least in part on a state of a phase change material included in the phase change layer. The phase change material of the phase change layer is in a first state of a set of states, and the waveguide has a first refractive index determined based on the first state of the phase change material. The heater is to generate heat to transform the phase change material to a second state of the set of states, and the waveguide has a second refractive index determined based on the second state of the phase change material. Other embodiments may also be described and claimed.

Abstract: Apparatus/method estimate LOS rotation, to track, approach, pursue, intercept or avoid objects. Vehicle-fixed imagers approach/recede-from objects, recording image series with background. Computations, from images exclusively, estimate rotation vs. the vehicle, applying the estimate. Preferably, recording/estimating provide proportional navigation; scan mirrors extend strapdown-sensor FOR; applying includes measuring “range rate over range”, exclusively from interimage optical flow, using results to optimize proportional-navigation loop gain; estimating includes evaluating interframe optical flow, preregistering roughly as first approximation, selecting sequence anchor points, and applying a second, finer technique developing output registration that's a coordinate translation, aligning inertial surroundings. The approximation operates optical flow with efficient embedded registration/mapping, applying a homography matrix to nearby imagery.

Abstract: A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures.

Abstract: A memory includes multiple layers of deposited memory material. An etch is performed on at least one layer of deposited memory material prior to the deposition of a subsequent layer of memory material.

Abstract: A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures.

Abstract: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.

Abstract: A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.

Abstract: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: In a phase change memory including an ovonic threshold switch, conduction around the phase change material layer in the ovonic threshold switch is reduced. In one embodiment, the reduction is achieved by undercutting the conductive layers on either side of the phase change material layer. In another embodiment, an angled ion implantation is carried out which damages the edge regions of the conductive layers that sandwich the phase change material layer.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract: The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes providing a lower electrode material in a recess. The method also includes removing at least a portion of the second side.

Abstract: The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is higher than in the lower section. A second dielectric film is disposed over the first dielectric film and has an upper surface that is coplanar with the upper section at an upper surface.

Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Abstract: A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does not. In another approach, a hard mask is used which is of substantially the same material as an overlying and surrounding insulator. The hard mask and an underlying phase change material are protected by a sidewall spacer of a different material than the hard mask. If the hard mask and the insulator have substantially the same etch characteristics, the hard mask may be removed while maintaining the protective character of the sidewall spacer.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, each of which may be refreshed under control of a refresh controller. In addition to the usual components of a DRAM, the cache memory system also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in the second bank. If, however, the second bank is being refreshed, the data are stored in the other SRAM.