Abstract: A method is provided for controlling the critical dimensions of a polysilicon gate electrode, and for improving transistor drive current control. The method involves subjecting the gate structure of a transistor to a thermal treatment process in the presence of hydrogen gas. The thermal treatment process is performed subsequent to gate etching and photoresist mask removal, and provides gate electrodes having a more homogeneous linewidth, thereby improving transistor performance.

Abstract: An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor.

Abstract: A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.

Abstract: A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.

Abstract: A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed.

Abstract: A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate.

Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: A dry etch process is presented wherein a semiconductor substrate is introduced into a reaction chamber between a first electrode and a second electrode. The semiconductor substrate may be positioned on the first electrode. A main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow at a fluorocarbon flow rate is established into the reaction chamber. RF power at a low frequency may then be applied to the first electrode for creating a fluorine-deficient plasma. An oxide layer arranged above the semiconductor substrate is exposed to the fluorine-deficient plasma for etching, in a single step, a portion of the oxide layer.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas. Each of the transistors has a gate dielectric layer with a V-shaped cross-section positioned on one of the plurality of active areas, a gate electrode positioned on the gate dielectric layer, a first source/drain region positioned in the substrate, and a second source/drain region positioned in the substrate in spaced-apart relation to the first source/drain region to define a channel region beneath the gate dielectric layer. The V-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate.

Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. The oxide having the greater thickness is formed adjacent a source or drain region of the device, and the oxide with the lesser thickness is formed adjacent the other one of the source or drain regions. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO.sub.2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO.sub.2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer.

Abstract: In a semiconductor device fabrication process, a first semiconductor device is constructed with a gate electrode and an active (e.g., source/drain) region. The thickness of the active region is determined. A second semiconductor device is constructed with the same gate electrode and active region dopant concentrations as the first device and is generally the same as the first device except for the thickness of the gate electrode. Using the determined thickness of the active region of the first device, the thickness of the gate electrode of the second device is controlled so that it differs from the thickness of the active region of the second device by a desired amount.

Abstract: A method and apparatus are provided for obtaining molecular information about materials at a selected site on or in a semiconductor topography. In a preferred embodiment, the selected site is a defect from a defect map generated by an automated wafer inspection system. A sample stage and drive/alignment system are used to move the semiconductor topography such that a selected defect is aligned with the illumination provided by a radiation scattering measurement system. A Raman spectroscopy system may be used for the radiation scattering measurement. The intensity and frequency of inelastically scattered radiation from the vicinity of the selected defect is compared to standard spectra to determine the chemical composition and material phase of the region analyzed. The depth into the topography probed may be adjusted by changing the wavelength of radiation used in the Raman spectroscopy measurement.

Abstract: The formation of a spacer for a graded dopant profile having a triangular geometry is disclosed. In one embodiment, a method has three steps. In the first step, a gate is formed on a substrate, the gate having two edges. In the second step, at least one spacer is formed, where each spacer is adjacent to an edge of the gate and has a triangular geometry. In the third step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer.

Abstract: A method is provided for fabricating a transistor gate conductor having opposed sidewall surfaces upon which dielectric spacers are formed such that the spacer profile substantially tapers toward the adjacent gate conductor sidewall surface as it approaches the base of the gate conductor. More particularly, formation of the sidewall spacers involves anisotropically etching a dielectric material deposited across a semiconductor topography in the presence of a passivant source to form a passivant upon portions of the dielectric material. The passivant primarily accumulates upon the upper portion of lateral surfaces of the dielectric material. An isotropic etch which occurs at the same rate in all directions is used to etch portions of the dielectric material not completely covered by the passivant. The resulting spacers have a varying thickness which decreases from top to bottom.

Abstract: The formation of selectively sized spacers is disclosed. One embodiment comprises a method including four steps. In the first step, at least one spacer for each of a plurality of gates is formed on a substrate, the plurality of gates including a first gate and at least one remaining gate, and each spacer adjacent to an edge of its corresponding gate. In the second step, a mask is applied to the first gate, including the spacers for the first gate. In the third step, the spacers for the remaining gates are etched. In the fourth step, the mask applied to the first gate, including the spacers for the first gate, is removed.

Abstract: A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.

Abstract: A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.

Abstract: A method is provided for obtaining a topography with a substantially planar upper surface. The profile of the upper surface of the semiconductor topography is first detected by a profile detection tool, such as a stylus profilometer. The profile detection tool creates a database to quantify the elevational variations across the upper surface of the semiconductor topography. The database is then provided to a control system of a deposition tool. The control system controls the deposition of a profile layer upon the upper surface of the semiconductor topography such that a thickness of the profile layer is a function of the elevation of the surface. In one embodiment, the control system controls a potential gradient across the semiconductor topography so as to cause more reactant species to be directed toward the more recessed regions of the topography. In another embodiment, the control system controls the opening and closing of valves disposed within a shower head above the semiconductor topography.

Abstract: A semiconductor device having a nitrogen-rich active region-channel interface and process for fabrication thereof is provided. The nitrogen-rich interface can, for example, can reduce the electric field potential in this region and reduce hot carrier injection effects. Consistent with one embodiment of the invention, a semiconductor device is provided having a substrate, at least one gate electrode disposed over the substrate and an active region disposed adjacent to gate electrode. The semiconductor device further includes a channel region extending from the active region beneath the gate electrode and a nitrogen-rich region disposed at an interface between the channel region and the active region. The nitrogen-rich region may, for example, be disposed at least in part in the channel region. The nitrogen-rich region may, for example, also be disposed at least part of the active region. Further, the active region may be disposed, for example, within the nitrogen-rich region.

Abstract: A process for formation of isolation trenches with high-k gate dielectrics. In an example embodiment, the process comprises depositing a high permittivity layer on the substrate. An isolation trench extending from the high permittivity layer into the substrate is etched at a selected location on the substrate. The high permittivity layer is then etched to a selected thickness, and gate electrodes are formed adjacent the trench on the high permittivity layer of the selected thickness. In another embodiment, the isolation trench is formed with an oxide liner using an NO anneal, and the high-K gate dielectric layer is optionally reduced in thickness.