Abstract: A color photo sensing structure, includes an array of multiple color photo sensing elements. The photo sensing structure includes a first pixel located laterally with respect to a second pixel in a substrate of a first conductivity. The first pixel includes a first doped region of a second conductivity formed in the substrate and a second doped region of a first conductivity formed in the substrate above the first doped region. The second pixel includes two doped regions formed in the substrate having a first conductivity and a second conductivity, respectively. The color photo sensing structure further includes a controller for sequentially providing a first photocurrent value of the first doped region, a second photocurrent value of both the first and second doped regions and a third photocurrent value of the two doped regions of the second pixel.

Abstract: A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: Interpolation along an axis is performed on a Correlation Surface Array that was created from counting the instances of difference (XOR) between corresponding pixels of single bit resolution images having trial displacements. The interpolation is performed by finding the intersection of two straight line segments that are identified by the shape of the cross section of the Correlation Surface along the axis of interest. In the case of nine trial shifts there are three values in such a cross section, and they may seen as representing three points whose abscissas are the pixel shift amounts minus one, no shift, and plus one, and whose ordinates are the corresponding correlation values. In situations where navigation (and interpolation) is possible, these three points will have certain properties. The ususal case is that two of the points determine one line having a slope m, and the other point determines the other line (assumed to have slope −m).

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

Abstract: Optical navigation upon grainy surfaces whose orientation is inclined at about 45° to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45° and 135° inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a transverse ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.

Abstract: A method and apparatus are provided for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more AC-coupled connections on a printed circuit board (PCB). Direct current (DC)-restore logic receives an AC-coupled signal that corresponds to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.

Abstract: Optical navigation upon grainy surfaces whose orientation is inclined at about 45° to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45° and 135° inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a transverse ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: Optical navigation upon grainy surfaces whose orientation is inclined at about 45° to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45° and 135° inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a transverse ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: A method and apparatus are provided for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more AC-coupled connections on a printed circuit board (PCB). Direct current (DC)-restore logic receives an AC-coupled signal that corresponds to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.

Abstract: Interpolation along an axis is performed on a Correlation Surface Array that was created from counting the instances of difference (XOR) between corresponding pixels of single bit resolution images having trial displacements. The interpolation is performed by finding the intersection of two straight line segments that are identified by the shape of the cross section of the Correlation Surface along the axis of interest. In the case of nine trial shifts there are three values in such a cross section, and they may seen as representing three points whose abscissas are the pixel shift amounts minus one, no shift, and plus one, and whose ordinates are the corresponding correlation values. In situations where navigation (and interpolation) is possible, these three points will have certain properties. The ususal case is that two of the points determine one line having a slope m, and the other point determines the other line (assumed to have slope −m).