Abstract: A color photo sensing structure, includes an array of multiple color photo sensing elements. The photo sensing structure includes a first pixel located laterally with respect to a second pixel in a substrate of a first conductivity. The first pixel includes a first doped region of a second conductivity formed in the substrate and a second doped region of a first conductivity formed in the substrate above the first doped region. The second pixel includes two doped regions formed in the substrate having a first conductivity and a second conductivity, respectively. The color photo sensing structure further includes a controller for sequentially providing a first photocurrent value of the first doped region, a second photocurrent value of both the first and second doped regions and a third photocurrent value of the two doped regions of the second pixel.

Abstract: A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage.

Abstract: Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.

Abstract: Optical navigation upon grainy surfaces whose orientation is inclined at about 45° to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45° and 135° inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a transverse ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A method and apparatus are provided for enabling a Joint Test Access Group (JTAG)-type EXTEST to be performed in an alternating current (AC)-coupled system in order to test one or more AC-coupled connections on a printed circuit board (PCB). Direct current (DC)-restore logic receives an AC-coupled signal that corresponds to an EXTEST test pattern output from a transmitting JTAG-compliant integrated circuit (IC), and converts the AC-coupled signal into a DC signal suitable for use by JTAG logic of a JTAG-compliant receiving IC.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: Interpolation along an axis is performed on a Correlation Surface Array that was created from counting the instances of difference (XOR) between corresponding pixels of single bit resolution images having trial displacements. The interpolation is performed by finding the intersection of two straight line segments that are identified by the shape of the cross section of the Correlation Surface along the axis of interest. In the case of nine trial shifts there are three values in such a cross section, and they may seen as representing three points whose abscissas are the pixel shift amounts minus one, no shift, and plus one, and whose ordinates are the corresponding correlation values. In situations where navigation (and interpolation) is possible, these three points will have certain properties. The ususal case is that two of the points determine one line having a slope m, and the other point determines the other line (assumed to have slope −m).

Abstract: Optically navigation upon grainy surfaces whose orientation is inclined at about 45° to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45° and 135° inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations.

Abstract: A pixel column amplifier architecture creates a reduced noise differential image signal from an pixel sensor array. The pixel column amplifier architecture comprises a first double sampling (DS) circuit and a second DS circuit that has the same configuration as the first DS circuit. An image signal containing a combination of noise components created on a substrate is coupled to the first DS circuit. A reference image signal, held in a reset state, represents the noise component of the image signal and is coupled to the second DS circuit. Further, a reference voltage source is coupled to a reference input of both the first DS and the second DS circuits. The first DS circuit provides the first side of the differential image signal, and the second DS circuit provides the second side of the differential image signal.

Abstract: A method and apparatus for scanning an original image with an optical scanning device and for constructing a duplication of the original image. The apparatus of the present invention comprises an optical scanning device for scanning the original image and for generating an electrical representation of the original image. The scanning device comprises an illumination device for projecting light onto an original image being scanned, an optical image sensing device disposed to receive light reflected from the original image, and a processing device in communication with the optical image sensing device for receiving electrical signals produced by the optical sensors of the optical image sensing device and for processing the electrical signals. The optical image sensing device comprises a plurality of optical sensors. Each optical sensor has a field of view and at least two of the optical sensors have fields of view which at least partially overlap.

Abstract: A spatial filter having coefficients selected and distributed within an array, so that when the array is divided non-diagonally into four equal quadrants, (1) the coefficients are of constant sign within each quadrant; (2) coefficients in diagonally opposed quadrants have like sign; and (3) coefficients in non-diagonally neighboring quadrants have unlike sign. In a preferred embodiment, coefficients cause the array to form a "saddle" shape when the coefficient values are representative of the local slope on a surface described by the array. This "saddle" shape enables improved filtration properties. The inventive spatial filter is further advantageously embodied in architecture comprising an array of individual calculation modules corresponding to the filter array. Rows of modules are coupled together in parallel. The input signal is fed to each row concurrently via FIFO buffers, enabling concurrent calculation operations.

Abstract: An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Abstract: This invention provides an apparatus and method of fabrication thereof for an inkjet printhead with an improved ink flow path between an ink reservoir and vaporization chambers in an inkjet printhead. In the preferred embodiment, a barrier layer containing ink channels and vaporization chambers is located between a rectangular substrate and a nozzle member containing an array of orifices. The substrate contains two linear arrays of heater elements, and each orifice in the nozzle member is associated with a vaporization chamber and heater element. The ink channels in the barrier layer have ink entrances generally running along two opposite edges of the substrate so that ink flowing around the edges of the substrate gain access to the ink channels and to the vaporization chambers. The apparatus is fabricated without using ion implant technology.

Abstract: A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs.