Abstract: Optically navigation upon grainy surfaces whose orientation is inclined at about 45° to the X and Y axes of the navigation mechanism is enhanced by: First, detect that a spatial filter in use is inappropriate for the orientation presently occurring, and; Second, employ a different and more appropriate spatial filter subsequent to such detection. Two spatial filters have been developed that are respectively effective about the 45° and 135° inclinations of the Standard filter. The shape of a correlation surface used in the navigation process is tested for the presence of a ridge in the correlation surface. This generates control metrics whose filtered excursions are tracked by a control system that changes the spatial filter in use. The control system incorporates a time constant to prevent thrashing and excessive sensitivity to isolated random variations.

Abstract: A pixel column amplifier architecture creates a reduced noise differential image signal from an pixel sensor array. The pixel column amplifier architecture comprises a first double sampling (DS) circuit and a second DS circuit that has the same configuration as the first DS circuit. An image signal containing a combination of noise components created on a substrate is coupled to the first DS circuit. A reference image signal, held in a reset state, represents the noise component of the image signal and is coupled to the second DS circuit. Further, a reference voltage source is coupled to a reference input of both the first DS and the second DS circuits. The first DS circuit provides the first side of the differential image signal, and the second DS circuit provides the second side of the differential image signal.

Abstract: A method and apparatus for scanning an original image with an optical scanning device and for constructing a duplication of the original image. The apparatus of the present invention comprises an optical scanning device for scanning the original image and for generating an electrical representation of the original image. The scanning device comprises an illumination device for projecting light onto an original image being scanned, an optical image sensing device disposed to receive light reflected from the original image, and a processing device in communication with the optical image sensing device for receiving electrical signals produced by the optical sensors of the optical image sensing device and for processing the electrical signals. The optical image sensing device comprises a plurality of optical sensors. Each optical sensor has a field of view and at least two of the optical sensors have fields of view which at least partially overlap.

Abstract: A spatial filter having coefficients selected and distributed within an array, so that when the array is divided non-diagonally into four equal quadrants, (1) the coefficients are of constant sign within each quadrant; (2) coefficients in diagonally opposed quadrants have like sign; and (3) coefficients in non-diagonally neighboring quadrants have unlike sign. In a preferred embodiment, coefficients cause the array to form a "saddle" shape when the coefficient values are representative of the local slope on a surface described by the array. This "saddle" shape enables improved filtration properties. The inventive spatial filter is further advantageously embodied in architecture comprising an array of individual calculation modules corresponding to the filter array. Rows of modules are coupled together in parallel. The input signal is fed to each row concurrently via FIFO buffers, enabling concurrent calculation operations.

Abstract: An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Abstract: This invention provides an apparatus and method of fabrication thereof for an inkjet printhead with an improved ink flow path between an ink reservoir and vaporization chambers in an inkjet printhead. In the preferred embodiment, a barrier layer containing ink channels and vaporization chambers is located between a rectangular substrate and a nozzle member containing an array of orifices. The substrate contains two linear arrays of heater elements, and each orifice in the nozzle member is associated with a vaporization chamber and heater element. The ink channels in the barrier layer have ink entrances generally running along two opposite edges of the substrate so that ink flowing around the edges of the substrate gain access to the ink channels and to the vaporization chambers. The apparatus is fabricated without using ion implant technology.

Abstract: A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A circuit provides a high impedance input to an operational amplifier by substituting a p-channel field effect transistor for the bias resistor normally used on the input to an operation amplifier. By placing a PFET in place of the bias resistor, a resistance value can be created that is hundreds of times higher, for the same area of silicon within the integrated circuit, as that created with an actual resistor. This PFET has parasitic capacitance which may be significantly offset by connecting the gate of the PFET to the output of a source follower circuit having its input connected to the inverting input of the operational amplifier. The circuit may be still further improved by using a voltage follower amplifier circuit in place of the source follower.

Abstract: A fully-integrated CMOS peak detector stores the peak amplitude of an input signal using an on-chip storage capacitor. The fully-integrated CMOS peak detector includes a delay buffer, a transfer gate and a comparator. A discharge controller is used to step-down the peak amplitude stored on the on-chip storage capacitor some predetermined amount. The discharge controller includes a switched capacitor circuit which is placed in series with the storage capacitor such that the two capacitors act as a capacitive voltage divider to produce a predictable fraction of the acquired peak amplitude. Multiple peaks can be determined and/or stored by using multiple fully-integrated CMOS peak detectors in conjunction with a single comparator. A multiplexer is used in this configuration to control the multiple peak detectors.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A latching CMOS comparator method and circuit are disclosed. The comparator circuit includes a differential input stage and a latching stage. The input stage includes a differential amplifier (MP3,MP4) and a Moore Mirror load. The load includes a first cross-coupled amplifier pair (MN3,MN4), and a pair of diode-connected transistors (MN1,MN2) coupled in parallel to the first amplifier to control gain. The input stage devices are sized to provide a gain on the order of 10 to 20. The latch clock signal (CLK) is isolated from the input stage to avoid injected charge offset error. The second or latching stage includes a second cross-coupled transistor amplifier (MP7,MP8) coupled to the input stage to provide additional gain. The latch clock signal is provided to a digital switch (MP9,MP10) which controls gain in the second amplifier.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: An improved thermal inkjet printhead having MOSFET drive transistors incorporated therein. The gate of each MOSFET transistor is formed by applying a layer of silicon dioxide onto a silicon substrate, applying a layer of silicon nitride onto the silicon dioxide, and applying a layer of polycrystalline silicon onto the silicon nitride. Portions of the substrate surrounding the gate are oxidized, forming field oxide regions. Drain and source regions are then conventionally formed, followed by the application of a protective dielectric layer onto the field oxide, drain, source, and gate. A resistive layer is deposited on the dielectric layer and directly connected to the source, drain, and gate. A conductive layer is deposited on a portion of the resistive layer, ultimately forming both covered and uncovered regions thereof. The uncovered region functions as a heating resistor, and the covered regions function as electrical contacts to the transistor and resistor.

Abstract: A pipe to plate connection for attaching light stools to an overhead structure on ships. A stud gun welds a stud into a plate. The stud is threaded and is received into a cylindrical insert force fit into a length of pipe. The insert is threaded and receives the stud. The insert also has at least one external circumferential groove. Upon the cylindrical insert being force fit into the end of the pipe, the circumferential grooves are covered by the pipe. The pipe is swaged into the grooves of the insert. A tensile force between the pipe and the plate may be formed by a spring washer between the pipe and the overhead. The insert may have the outer surface deformed as by knurling to deform the inside of the pipe upon its insertion to aid in prevention of rotational movement between the insert and the pipe.

Abstract: Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.

Abstract: A nonlinear noninverting amplifier design for receiving and amplifying an input signal in an optical communication scheme having a nonlinear inverting feedback is disclosed. The inverting feedback varies nonlinearly with the input signal to avoid saturation of the amplifier while providing a zero state input amplitude signal to reduce the amplitude of the input signal required to turn-on the feedback, thus allowing the amplifier to operate with a wide variation of optical generators, paths, and converters. A nonlinear noninverting amplifier design is provided which eliminates the need for automatic gain control circuitry and can be designed as an integrated circuit.