Abstract: This is a method of fabricating a lateral gate, vertical drift region transistor including a semiconductor substrate having a drain on the reverse surface. A doped semiconductor layer is formed on the substrate and a high resistivity region is formed adjacent the surface of the doped layer so as to define a vertical drift region in the doped layer. A lateral channel is formed on the high resistivity region and the doped layer so as to communicate with the vertical drift region. A source is positioned on the lateral channel spaced laterally from the vertical drift region and a gate is positioned on the lateral channel between the drift region and the source.

Abstract: A gallium arsenide amplifier (10) utilizes a P-channel heterojunction transistor (12) and an N-channel heterojunction transistor (11) connected in a stacked configuration. The gate width of the P-channel heterojunction transistor is scaled so that the transconductance of the P-channel heterojunction transistor approximately equals the transconductance of the N-channel heterojunction transistor. The gate length (44) of the N-channel heterojunction transistor is scaled so that the input impedance of the N-channel heterojunction transistor approximately equals the input impedance of the P-channel heterojunction transistor.

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an accumulation region extending laterally adjacent the control terminal and communicating with the drift region and the source.

Abstract: A FET including a channel region and a drift region in a channel layer with a source in the channel region and a drain in the drift region. The current channel between the source and drain defining a straight transistor portion and a curved transistor portion. An oxide with a thin portion overlying the channel region and a thick portion overlying the drift region, and a gate on the thin oxide overlying the current channel. A drain field plate and a gate field plate on the thick oxide with spaced apart edges and a damaged region underlying the edges of the field plates only in the curved transistor portion to reduce electric fields at the edges of the field plates. Also, the current channel has a greater length and the edges are spaced apart farther in the curved transistor portions.

Abstract: A lateral MESFET (10,20) utilizes a drain (17) and a source (18) damage termination layer to improve the breakdown voltage of the MESFET (10,20). The source (18) and drain (17) damage termination layers are very shallow to prevent interfering with lateral current flow in the channel layer (12). The source (18) and drain (17) damage termination layers are formed by implanting large inert ions using high implant doses and low implantation energies.

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: A silicon carbide MOSFET (10) is formed to have a high breakdown voltage. A breakdown enhancement layer (20) is formed between a channel region (14) and a drift layer (12). The breakdown enhancement layer (20) has a lower doping concentration that increases the width of a depletion region (24) near a gate insulator (17). The increased depletion region width improves the breakdown voltage.

Abstract: An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).

Abstract: A silicon carbide LOCOS vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor regions, rather than defining the regions with implants and diffusion. Because of the low diffusion rate in silicon carbide, the LOCOS operation can be performed after the doped epitaxial layers are formed.

Abstract: A lateral silicon carbide transistor (10) utilizes a modulated channel region (18) to form an accumulation region that facilitates a low on-resistance. A doped region of the channel layer forms a channel insert (14) that also lowers the on-resistance of the transistor (10). Field plates (23,24) are utilized to facilitate providing a high breakdown voltage. A high resistance layer (29)between the field plates (23,24) also assists in increasing the breakdown voltage and decreasing on-resistance of the transistor (10).

Abstract: A method of fabricating a semiconductor device including forming a Schottky contact on the surface of a substrate by patterning a layer of nickel to define a contact and annealing the nickel below approximately 600.degree. C. A trench is etched around the Schottky contact utilizing the Schottky contact as an etch mask and inert ions are implanted in the trench to form a damage region. The trench is passivated with a dielectric layer. An ohmic contact can be formed on the reverse side of the substrate prior to formation of the Schottky contact.

Abstract: A lateral silicon carbide transistor (10) utilizes a modulated channel region (18) to form an accumulation region that facilitates a low on-resistance. A doped region of the channel layer forms a channel insert (14) that also lowers the on-resistance of the transistor (10). A damage termination layer (27) is utilized to facilitate providing a high breakdown voltage. Field plates (23,24) also assists in increasing the breakdown voltage and decreasing the on-resistance of the transistor (10).

Abstract: A silicon carbide vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor electrodes, rather than defining the electrodes with implants and diffusion. An opening is formed in some of the epitaxial layers and a conductive layer is formed therein to electrically connect a drain contact on the rear of the substrate to the components on the front of the substrate.

Abstract: A modulation doped field effect transistor (10) is formed to have a drain (28, 12, 11) that is vertically displaced from the source (16, 17) and channel (20, 21) regions. The transistor (10) has the source (16, 17), channel (20, 21) and a portion of the drain (28) arranged laterally so that current (27) flows from the source (16, 17) laterally to the drain (28, 12, 11). A heterojunction layer (18) on the channel region (20, 21) facilitates forming a two dimensional electron gas in the channel (20, 21) region which provides the transistor (10) with a high transconductance.

Abstract: A diode protected semiconductor device appropriate for the output of a radio frequency amplifier, which can withstand substantial power reflection due to output impedance mismatch, is provided. The device may be implemented monolithically, in the form of a field effect transistor (FET) (14) having a back to back diode pair (17) connecting the drain (18) to the source (19). The FET comprises multiple transistor portions (28) coupled together. The diode pair comprises corresponding diode pair portions (37) coupled together. The configuration provides easy integration of the diode pair (17) into typical FET structures.

Abstract: A silicon carbide LOCOS vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor electrodes, rather than defining the electrodes with implants and diffusion. Because of the low diffusion rate in silicon carbide, the LOCOS operation can be performed after the doped epitaxial layers are formed.

Abstract: A silicon carbide vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor electrodes, rather than defining the electrodes with implants and diffusion. An opening is formed in some of the epitaxial layers and a conductive layer is formed therein to electrically connect a drain contact on the rear of the substrate to the components on the front of the substrate.

Abstract: A gate-drain shield is used to reduce the gate to drain capacitance of a transistor. The gate-drain shield is formed as a conductor that is positioned on the surface of the transistor between the gate and the drain. The conductor is formed on an insulator thereby electrically insulating the conductor from the substrate of the transistor.

Abstract: A hypoeutectic ohmic contact to gallium arsenide comprising a refractory metal layer is provided which reduces the outdiffusion of gallium and arsenic which would otherwise be seen as impurities at the outer surface of the ohmic contact.