Patents by Inventor Charles F. Musante
Charles F. Musante has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8409904Abstract: Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.Type: GrantFiled: June 21, 2011Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Patent number: 8409899Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.Type: GrantFiled: February 11, 2011Date of Patent: April 2, 2013Assignee: Intnernational Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Charles F. Musante, Richard J. Rassel
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Patent number: 8298853Abstract: CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.Type: GrantFiled: August 10, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Rajendran Krishnasamy, Solomon Mulugeta, Charles F. Musante, Richard J. Rassel
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Patent number: 8233070Abstract: A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.Type: GrantFiled: September 3, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Mark D. Jaffe, Charles F. Musante
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Publication number: 20120168835Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Patent number: 8138534Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.Type: GrantFiled: April 29, 2010Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Publication number: 20120037967Abstract: CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.Type: ApplicationFiled: August 10, 2010Publication date: February 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. ADKISSON, John J. ELLIS-MONAGHAN, Rajendran KRISHNASAMY, Solomon MULUGETA, Charles F. MUSANTE, Richard J. RASSEL
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Publication number: 20120018832Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.Type: ApplicationFiled: July 22, 2010Publication date: January 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. COONEY, III, Jeffrey P. GAMBINO, Robert K. LEIDY, Charles F. MUSANTE, John G. TWOMBLY
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Publication number: 20110250715Abstract: Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.Type: ApplicationFiled: June 21, 2011Publication date: October 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Patent number: 8023021Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.Type: GrantFiled: December 18, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Mark D. Jaffe, Charles F. Musante, Richard J. Rassel
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Patent number: 8009216Abstract: A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.Type: GrantFiled: July 16, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Rajendran Krishnasamy, Solomon Mulugeta, Charles F. Musante, Richard J. Rassel
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Patent number: 8009215Abstract: A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.Type: GrantFiled: July 16, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Rajendran Krishnasamy, Solomon Mulugeta, Charles F. Musante, Richard J. Rassel
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Patent number: 8003425Abstract: Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.Type: GrantFiled: May 14, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Publication number: 20110129955Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.Type: ApplicationFiled: February 11, 2011Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Charles F. Musante, Richard J. Rassel
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Patent number: 7928527Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.Type: GrantFiled: June 4, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Charles F. Musante, Richard J. Rassel
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Publication number: 20100264473Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.Type: ApplicationFiled: April 29, 2010Publication date: October 21, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Publication number: 20100245644Abstract: A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.Type: ApplicationFiled: September 3, 2009Publication date: September 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. Ellis-Monaghan, Mark D. Jaffe, Charles F. Musante
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Patent number: 7759755Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.Type: GrantFiled: May 14, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Publication number: 20100097511Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.Type: ApplicationFiled: December 18, 2009Publication date: April 22, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. Adkisson, John J. Ellis-Monaghan, Mark D. Jaffe, Charles F. Musante, Richard J. Rassel
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Patent number: 7655966Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.Type: GrantFiled: March 19, 2008Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Mark D. Jaffe, Charles F. Musante, Richard J. Rassel