Patents by Inventor Charles F. Webb

Charles F. Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10977190
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
  • Patent number: 10970224
    Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elpida Tzortzatos, Steven M. Partlow, Scott B. Compton, Christine Michele Yost, Charles F. Webb, Christian Jacobi
  • Patent number: 10884946
    Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pak-kin Mak, Timothy J. Slegel, Craig R. Walters, Charles F. Webb
  • Patent number: 10884945
    Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pak-kin Mak, Timothy J. Slegel, Craig R. Walters, Charles F. Webb
  • Publication number: 20200409857
    Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Elpida Tzortzatos, Steven M. Partlow, Scott B. Compton, Christine Michele Yost, Charles F. Webb, Christian Jacobi
  • Patent number: 10635308
    Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Peter G. Sutton, Craig R. Walters, Charles F. Webb
  • Patent number: 10635307
    Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Peter G. Sutton, Craig R. Walters, Charles F. Webb
  • Publication number: 20190303301
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Applicant: International Business Machines Corporation
    Inventors: Dan F. GREINER, Charles W. GAINEY, Jr., Lisa C. HELLER, Damian L. OSISEK, Erwin PFEFFER, Timothy J. SLEGEL, Charles F. WEBB
  • Patent number: 10423539
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
  • Patent number: 10338923
    Abstract: A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philip G. Emma, Allan M. Hartstein, Keith N. Langston, Brian R. Prasky, Thomas R. Puzak, Charles F. Webb
  • Patent number: 9934159
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
  • Publication number: 20180089103
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Dan F. GREINER, Charles W. Gainey, JR., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
  • Publication number: 20170003884
    Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 5, 2017
    Inventors: Pak-kin Mak, Timothy J. Slegel, Craig R. Walters, Charles F. Webb
  • Publication number: 20170003886
    Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Pak-kin Mak, Timothy J. Slegel, Craig R. Walters, Charles F. Webb
  • Publication number: 20170003893
    Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 5, 2017
    Inventors: Jane H. Bartik, Peter G. Sutton, Craig R. Walters, Charles F. Webb
  • Publication number: 20170003882
    Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Jane H. Bartik, Peter G. Sutton, Craig R. Walters, Charles F. Webb
  • Publication number: 20160267017
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 15, 2016
    Applicant: International Business Machines Corporation
    Inventors: Dan F. GREINER, Charles W. GAINEY, JR., Lisa C. HELLER, Damian L. OSISEK, Erwin PFEFFER, Timothy J. SLEGEL, Charles F. WEBB
  • Patent number: 9411599
    Abstract: Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Jacobi, Barry W. Krumm, Brian R. Prasky, Martin Recktenwald, Chung-Lung K. Shum, Charles F. Webb, Joshua M. Weinberg
  • Patent number: 9378128
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
  • Patent number: 9250915
    Abstract: Data operand fetching control includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The data operand fetching control also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control. Each memory access control specifies a manner of handling data fetching operations. The data operand fetching control further includes performing a memory access operation for the selected instruction based upon the mapping.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Barry W. Krumm, Brian R. Prasky, Martin Recktenwald, Chung-Lung K. Shum, Charles F. Webb, Joshua M. Weinberg