Patents by Inventor Charles F. Webb
Charles F. Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9244856Abstract: An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.Type: GrantFiled: December 19, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J Siegel, Charles F Webb
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Publication number: 20150169437Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Inventors: Dan F. GREINER, Charles W. GAINEY, JR., Lisa C. HELLER, Damian L. OSISEK, Erwin PFEFFER, Timothy J. SLEGEL, Charles F. WEBB
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Patent number: 9052889Abstract: A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.Type: GrantFiled: December 26, 2012Date of Patent: June 9, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Jacobi, Marcel Mitran, Timothy J Slegel, Charles F Webb
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Patent number: 9021225Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.Type: GrantFiled: December 31, 2013Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
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Patent number: 9003134Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.Type: GrantFiled: December 30, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J Slegel, Charles F Webb
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Patent number: 8862834Abstract: Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed.Type: GrantFiled: July 25, 2013Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Donald W. Schmidt, Jaya Srikrishnan, Charles F. Webb, Leslie W. Wyman
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Patent number: 8850166Abstract: A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.Type: GrantFiled: February 18, 2010Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Christian Jacobi, Marcel Mitran, Timothy J. Slegel, Charles F. Webb
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Publication number: 20140188452Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.Type: ApplicationFiled: December 30, 2013Publication date: July 3, 2014Applicant: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
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Publication number: 20140181463Abstract: An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.Type: ApplicationFiled: December 19, 2013Publication date: June 26, 2014Applicant: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
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Publication number: 20140115295Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.Type: ApplicationFiled: December 31, 2013Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. GREINER, Charles W. GAINEY, JR., Lisa C. HELLER, Damian L. OSISEK, Erwin PFEFFER, Timothy J. SLEGEL, Charles F. WEBB
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Patent number: 8677098Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.Type: GrantFiled: January 11, 2008Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
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Patent number: 8631216Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.Type: GrantFiled: January 9, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J Siegel, Charles F Webb
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Patent number: 8621180Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.Type: GrantFiled: December 23, 2011Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
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Publication number: 20130311726Abstract: Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed.Type: ApplicationFiled: July 25, 2013Publication date: November 21, 2013Applicant: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Donald W. Schmidt, Jaya Srikrishnan, Charles F. Webb, Leslie W. Wyman
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Patent number: 8549255Abstract: A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.Type: GrantFiled: February 15, 2008Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: David A. Schroter, Mark S. Farrell, Jennifer Navarro, Chung-Lung Kevin Shum, Charles F. Webb
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Patent number: 8527715Abstract: A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed.Type: GrantFiled: February 26, 2008Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Donald W. Schmidt, Jaya Srikrishnan, Charles F. Webb, Leslie W. Wyman
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Patent number: 8407453Abstract: Processing within a computing environment is facilitated using an extended DRAIN instruction. An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.Type: GrantFiled: October 14, 2011Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, Bruce C. Giamei, Timothy J. Slegel, Charles F. Webb
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Patent number: 8380907Abstract: A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.Type: GrantFiled: February 26, 2008Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Lisa C. Heller, Damian L. Osisek, Charles F. Webb
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Publication number: 20120144153Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.Type: ApplicationFiled: January 9, 2012Publication date: June 7, 2012Applicant: International Business Machines CorporationInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
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Publication number: 20120137106Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.Type: ApplicationFiled: December 23, 2011Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb