Patents by Inventor Charles Hampton
Charles Hampton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060215727Abstract: A temperature regulation system with an integrated electrical generator is disclosed. In an exemplary embodiment, the temperature regulation system includes a combustion unit for producing heat energy. Further, a blower is in fluid communication with the combustion unit for dispersing air. Additionally, the integrated electrical generator is communicatively coupled to the combustion unit and the blower for providing electrical energy to the blower and the combustion unit. A flue is coupled to the combustion unit for drawing combustion waste products to an exterior environment. Furthermore, an exhaust system is coupled to at least one of the integrated electrical generator and the flue for drawing combustion waste products from the integrated electrical generator to an exterior environment. The integrated electrical generator is configured to provide electricity to the blower and the combustion unit upon interruption of the utility electrical energy supply to the temperature regulation system.Type: ApplicationFiled: January 17, 2006Publication date: September 28, 2006Inventor: Charles Hampton
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Patent number: 6988310Abstract: A method of assembling an interconnect device assembly which consists of cylindrical resilient wire bundles captured within a carrier. In a step of the method, the interconnect device assembly is placed in a fixture and the ends of the resilient wire bundles are deformed by shaping dies in the fixture so that the resilient wire bundles now have a dog bone shape. The dog bone shape of the resilient wire bundles prevents the resilient wire bundles from being partially or totally dislodged during handling and transit.Type: GrantFiled: June 28, 2002Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Gerald G. Advocate, Jr., Norman D. Curry, Francis Krug, David C. Long, Daniel O'Connor, Charles Hampton Perry, Robert Weiss
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Patent number: 6711810Abstract: A method in which an alignment tool consisting of a nest and guide tool is used to align an LGA module in the nest and then the LGA module is removed from the nest and aligned with a circuit card by the use of the guide tool.Type: GrantFiled: September 19, 2001Date of Patent: March 30, 2004Assignee: International Business Machines CorporationInventors: Todd H. Buley, Roger Lam, Daniel O'Connor, Charles Hampton Perry
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Publication number: 20040002233Abstract: A method of assembling an interconnect device assembly which consists of cylindrical resilient wire bundles captured within a carrier. In a step of the method, the interconnect device assembly is placed in a fixture and the ends of the resilient wire bundles are deformed by shaping dies in the fixture so that the resilient wire bundles now have a dog bone shape. The dog bone shape of the resilient wire bundles prevents the resilient wire bundles from being partially or totally dislodged during handling and transit.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald G. Advocate, Norman D. Curry, Francis Krug, David C. Long, Daniel O'Connor, Charles Hampton Perry, Robert Weiss
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Publication number: 20030051338Abstract: A method in which an alignment tool consisting of a nest and guide tool is used to align an LGA module in the nest and then the LGA module is removed from the nest and aligned with a circuit card by the use of the guide tool.Type: ApplicationFiled: September 19, 2001Publication date: March 20, 2003Applicant: International Business Machines CorporationInventors: Todd H. Buley, Roger Lam, Daniel O'Connor, Charles Hampton Perry
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Patent number: 6351134Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.Type: GrantFiled: May 7, 1999Date of Patent: February 26, 2002Assignee: International Business Machines CorporationInventors: James Marc Leas, Robert William Koss, Jody John Van Horn, George Frederick Walker, Charles Hampton Perry, David Lewis Gardell, Steve Leo Dingle, Ronald Prilik
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Publication number: 20020003432Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.Type: ApplicationFiled: May 7, 1999Publication date: January 10, 2002Inventors: JAMES MARC LEAS, ROBERT WILLIAM KOSS, JODY JOHN VAN HORN, GEORGE FREDERICK WALKER, CHARLES HAMPTON PERRY, DAVID LEWIS GARDELL, STEVE LEO DINGLE, RONALD PRILIK
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Patent number: 6174175Abstract: An electrical connector or interposer for making connection in a high density device electronic environment. The connector is made of a high density array of nickel columns held in a layer of polyimide with each column extending beyond the opposing surfaces of said layer of polyimide. The connector may be used to make temporary or permanent connection to electrical contacts without alignment. Connection may be accomplished by loading forces sufficient to form either an indentation or a penetration of solder ball contacts. Contact to a single chip or a full wafer of chips is facilitated for testing.Type: GrantFiled: April 29, 1999Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Alex A. Behfar, Dale Curtis McHerron, Charles Hampton Perry
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Patent number: 6020750Abstract: A plurality of multilayer glass-ceramic substrates are arranged in coplanar relationship in a tile pattern within a support platform. The glass-ceramic substrates and the support platform are both formed of materials having thermal expansion characteristics substantially equal to that of a wafer which is supported by the coplanarly aligned substrates during test and burn-in of the wafer. The present invention effectively solves the problem of providing a single large support member for wafer test and burn-in, which heretofore have been limited in mechanical properties and power capability.Type: GrantFiled: June 26, 1997Date of Patent: February 1, 2000Assignee: International Business Machines CorporationInventors: Daniel George Berger, James Noel Humenik, Mark Raymond LaForce, Charles Hampton Perry
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Patent number: 5976710Abstract: A multilevel high density interconnect structure of a semiconductor device or package including a substrate having at least one conductive feature therein, a film of a polyimide composition on the substrate and selected from the group consisting of a cured product of a polyamic acid and a cured product of a polyamic ester. The polyamic acid is prepared by reacting a stoichiometric excess of a linear aromatic diamine and aromatic dianhydride to form a first reaction product where the molar ratio of said diamine to said aromatic anhydride is in the range from 100:97 to 100:99.5 and then reacting the first reaction product with an aromatic anhydride. The polyamic ester is prepared by reacting a stoichiometric excess of a linear aromatic diamine and an aromatic diester diacyl chloride to form a second reaction product where the molar ratio of said diamine to said diester diacyl chloride is in the range from 100:97 to 100:99.5 and then reacting the second reaction product with aromatic anhydride.Type: GrantFiled: April 10, 1997Date of Patent: November 2, 1999Assignee: International Business Machines CorporationInventors: Krishna Gandhi Sachdev, John Patrick Hummel, Sundar Mangalore Kamath, Robert Neal Lang, Anton Nendaic, Charles Hampton Perry, Harbans Sachdev
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Patent number: 5977787Abstract: A multiple-chip probe assembly suitable for wafer testing over a wide temperature range includes a plurality of individual buckling beam probe elements. A support structure supports the plurality of buckling beam probe elements in an arrangement in accordance with an electrical contact footprint for use in electrically contacting multiple chips of a wafer under test and enables buckling movement in a contacting direction of the plurality of buckling beams. The support structure includes a principal support material having a thermal coefficient of expansion (TCE) matched with the wafer under test and a second material other than the principal support material, wherein a contact positioning of the plurality of buckling beam probe elements upon the wafer under test during a testing operation is maintained. The second material prevents an individual probe element from electrically contacting the principal support material.Type: GrantFiled: June 16, 1997Date of Patent: November 2, 1999Assignee: International Business Machines CorporationInventors: Gobina Das, Paul Mathew Gaschke, Suryanarayan G. Hegde, Mark Raymond LaForce, Dale Curtis McHerron, Charles Hampton Perry, Frederick L. Taber, Jr.
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Patent number: 5929651Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.Type: GrantFiled: November 18, 1996Date of Patent: July 27, 1999Assignee: International Business Machines CorporationInventors: James Marc Leas, Robert William Koss, Jody John Van Horn, George Frederick Walker, Charles Hampton Perry, David Lewis Gardell, Steve Leo Dingle, Ronald Prilik
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Patent number: D338889Type: GrantFiled: December 20, 1990Date of Patent: August 31, 1993Assignee: International Telecommunication Corp.Inventors: Jerry W. Fuqua, Charles Hampton