Patents by Inventor Charles Ingalls
Charles Ingalls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090129176Abstract: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.Type: ApplicationFiled: December 11, 2008Publication date: May 21, 2009Inventors: Huy Vo, Charles Ingalls
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Patent number: 7535282Abstract: The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.Type: GrantFiled: June 7, 2005Date of Patent: May 19, 2009Assignee: Micron Technology, Inc.Inventors: Tae Kim, Howard Kirsch, Charles Ingalls, David Pinney
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Patent number: 7480202Abstract: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.Type: GrantFiled: February 22, 2008Date of Patent: January 20, 2009Assignee: Micron Technology, Inc.Inventors: Huy Vo, Charles Ingalls
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Publication number: 20080225624Abstract: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.Type: ApplicationFiled: February 22, 2008Publication date: September 18, 2008Inventors: Huy Vo, Charles Ingalls
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Patent number: 7352649Abstract: A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.Type: GrantFiled: July 21, 2005Date of Patent: April 1, 2008Assignee: Micron Technology, Inc.Inventors: Huy Vo, Charles Ingalls
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Publication number: 20080035803Abstract: A utility bucket has a second bottom attached by a hinge to the first bottom. Adjustable locking rods slide in tracks at one end to adjust the angle of the second bottom relative to the first bottom to maintain the bucket in a vertical orientation for any roof angle.Type: ApplicationFiled: August 3, 2006Publication date: February 14, 2008Inventor: Charles Ingalls
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Publication number: 20070299092Abstract: The present invention provides for compounds with the general formula: A compound of formula (1) having the structure (1) wherein Z is a radical selected from the group (a), (b), or (c) as well as methods and compositions containing these compounds useful for treatment of diseases that are characterized, at least in part, by excessive, abnormal, or inappropriate angiogenesis. These disease states, include but are not limited to, cancer, diabetic retinopathy, macular degeneration and rheumatoid arthritis. These compounds inhibit angiogenesis by inhibiting a tyrosine kinase receptor enzyme, specifically KDR, and binding to the KDR in an irreversible manner.Type: ApplicationFiled: May 11, 2005Publication date: December 27, 2007Applicant: WyethInventors: Middleton Floyd Jr, Thomas Nittoli, Allan Wissner, Russell Dushin, Ramaswamy Nilakantan, Charles Ingalls, Heidi Fraser, Bernard Johnson
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Publication number: 20070019486Abstract: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.Type: ApplicationFiled: July 21, 2005Publication date: January 25, 2007Inventors: Huy Vo, Charles Ingalls
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Publication number: 20060274596Abstract: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.Type: ApplicationFiled: August 1, 2006Publication date: December 7, 2006Inventors: Tae Kim, Charles Ingalls, Howard Kirsch, Jeremy Gum
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Publication number: 20060273842Abstract: In one embodiment of the invention, the p- well back bias for the NCH transistors in a DRAM sense amplifier circuit are dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amps is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well.Type: ApplicationFiled: June 7, 2005Publication date: December 7, 2006Applicant: Micron Technology, Inc.Inventors: Tae Kim, Howard Kirsch, Charles Ingalls, David Pinney
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Publication number: 20060268639Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.Type: ApplicationFiled: August 7, 2006Publication date: November 30, 2006Inventors: Sei Yoon, Charles Ingalls, David Pinney, Howard Kirsch
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Publication number: 20060268638Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.Type: ApplicationFiled: August 7, 2006Publication date: November 30, 2006Inventors: Sei Yoon, Charles Ingalls, David Pinney, Howard Kirsch
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Publication number: 20060268640Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.Type: ApplicationFiled: August 7, 2006Publication date: November 30, 2006Inventors: Sei Yoon, Charles Ingalls, David Pinney, Howard Kirsch
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Publication number: 20060262636Abstract: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.Type: ApplicationFiled: August 1, 2006Publication date: November 23, 2006Inventors: Tae Kim, Charles Ingalls, Howard Kirsch, Jeremy Gum
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Publication number: 20060198220Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.Type: ApplicationFiled: March 7, 2005Publication date: September 7, 2006Inventors: Sei Yoon, Charles Ingalls, David Pinney, Howard Kirsch
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Publication number: 20060044921Abstract: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.Type: ApplicationFiled: August 27, 2004Publication date: March 2, 2006Inventors: Tae Kim, Charles Ingalls, Howard Kirsch, Jeremy Gum
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Publication number: 20050077916Abstract: An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.Type: ApplicationFiled: October 18, 2004Publication date: April 14, 2005Inventors: Richard Mecier, Charles Ingalls