Abstract: An apparatus, according to one embodiment, includes: one or more memory devices, each memory device comprising non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices. The memory controller is configured to: detect at least one read of a logical page straddled across codewords, store an indication of a number of detected reads of the straddled logical page, and relocate the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A system, according to one embodiment, includes: non-volatile memory; a non-volatile memory controller having a cache; and logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to: retrieve a physical block address corresponding to a logic block address; extract information from the physical block address; perform a lookup operation in cache using the extracted information; perform a range check of the physical block address in response to the lookup operation succeeding; and read data from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, in addition to supporting parallel writes to different non-volatile memory channels. The cache architecture also supports pipelining of the parallel writes to different non-volatile memory planes. The non-volatile memory controller is also configured to perform a direct memory lookup in the cache based on a physical block address.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: A computer-implemented method, according to one embodiment, includes: repeating the following sequence at least until a page stripe of a memory cache has at least a predetermined amount of data stored therein: finding an open codeword having an amount of available space which is greater than or equal to a size of a compressed logical page, and storing the compressed logical page in the open codeword having the amount of available space which is greater than or equal to a size of the compressed logical page. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports separation of data streams, and the cache architecture supports parallel writes to different non-volatile memory channels. Additionally, the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes. Furthermore, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: In a data storage system, a prior set S of prefix codes for pseudo-dynamic compression as well as data compressed utilizing prior set S are stored. While data compressed utilizing prior set S are stored in the data storage system, the number of prefix codes utilized by the data storage system for pseudo-dynamic compression are augmented. Augmenting the number of codes includes determining a new set S? of prefix codes for pseudo-dynamic compression from a training data set selected from a workload of the data storage system and storing the new set S? in the data storage system with the prior set S.

Abstract: A technique for garbage collection in a storage system includes generating regrouping metadata for one or more pages of at least two logical erase blocks (LEB). The regrouping metadata indicates an associated stream for each of the pages. Multiple of the LEBs that include valid pages associated with a first stream are selected, based on the regrouping metadata, for regrouping. The valid pages associated with the first stream from the selected LEBs are regrouped into a new LEB.

Abstract: A technique for adapting over-provisioning space in a storage system includes determining one or more workload characteristics in the storage system. Over-provisioning space in the storage system is then adjusted to achieve a target write amplification for the storage system, based on the workload characteristics.

Abstract: A computer-implemented method, according to one embodiment, includes: repeating the following sequence at least until a page stripe of a memory cache has at least a predetermined amount of data stored therein: finding an open codeword having an amount of available space which is greater than or equal to a size of a compressed logical page, and storing the compressed logical page in the open codeword having the amount of available space which is greater than or equal to a size of the compressed logical page. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: In response to receipt of a write input-output operation (IOP) including a logical address and a logical page of write data, control logic of a data storage system detects a presence of a data pattern in the logical page. In response to detecting the presence of the data pattern in the logical page of write data, the control logic records, in a logical-to-physical translation data structure, an association between the logical address and a data pattern identifier identifying the detected data pattern in the bulk storage media, refrains from writing the logical page of write data to the bulk storage media, and writes logical page metadata describing the logical page of write data to the bulk storage media. The logical page metadata includes at least the logical address and the data pattern identifier, such that contents of the logical-to-physical translation data structure can be recovered from the bulk storage media.

Abstract: A mechanism is provided in a non-volatile memory controller for reducing read access latency by straddling pages across non-volatile memory channels. Responsive to a request to write a logical page to a non-volatile memory array, the non-volatile memory controller determines whether the logical page fits into a current physical page. Responsive to determining the logical page does not fit into the current physical page, the non-volatile memory controller writes a first portion of the logical page to a first physical page in a first block and writes a second portion of the logical page to a second physical page in a second block. The first physical page and the second physical page are on different non-volatile memory channels.

Abstract: A multidimensional storage array (SA) system includes storage elements (SEs) arranged in storage array partitions, a plurality of input shifters, and a plurality of output shifters. One respective input shifter and output shifter is associated with one partition. The SEs are arranged into rows and columns and each store particular bit(s) of a data word. Each of the input shifters implements a positional shift to a data word that is then loaded to the associated partition. Each of the output shifters unloads a loaded data word, reverses the positional shift of the unloaded data word, and provides the data word to a requesting device, such as a decoder. The loaded data words are exposed so that multiple row or column addressed data words may be unloaded from the SA simultaneously in a single clock cycle. Multiple column or row address data word segments may be physically diagonally arranged within each storage array partition.

Abstract: A method, according to one embodiment, includes repeating the following sequence at least until a page stripe of a memory cache has at least a predetermined amount of data stored therein: receiving a compressed logical page of data, finding an open codeword having an amount of available space which is greater than or equal to a size of the compressed logical page, and storing the compressed logical page in the open codeword having the amount of available space which is greater than or equal to a size of the compressed logical page. The compressed logical page does not straddle out of the open codeword. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining, by a processor, a first open logical erase block for user writes; maintaining, by the processor, a second open logical erase block for relocate writes; receiving, by the processor, a first data stream having the user writes; transferring, by the processor, the first data stream to the first open logical erase block; receiving, by the processor, a second data stream having the relocate writes; and transferring, by the processor, the second data stream to the second open logical erase block. Moreover, the first and second open logical erase blocks are different logical erase blocks. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of blocks of physical memory, each including multiple pages. The data storage system further includes a controller that maintains a data structure identifying blocks of physical memory in the memory array that currently do not store valid data. The controller, responsive to receipt of a write input/output operation (IOP) specifying an address and write data, selects a particular block from among the blocks identified in the data structure prior to a dwell time threshold for the particular block being satisfied, programs a page within the selected block with the write data, and associates the address with the selected block.

Abstract: In at least one embodiment, a non-volatile memory array including a plurality of blocks each including a plurality of physical pages is controlled by a controller. The controller implements a plurality of nested page retirement classes each defined by a respective one of a plurality of different nested subsets of page indices of physical pages within the plurality of blocks that are to be considered retired from use. For each block among the plurality of blocks, the controller updating an indication of a page retirement class to which the block belongs in response to detection of a retirement-causing error in a data page stored in a physical page of the block. The controller forms block stripes for storing data from the plurality of blocks based on the page retirement classes of the blocks.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: An apparatus, according to one embodiment, includes: one or more memory devices, each memory device comprising non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices. The memory controller is configured to: detect at least one read of a logical page straddled across codewords, store an indication of a number of detected reads of the straddled logical page, and relocate the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.