Abstract: A sense amplifier circuit that decreases the write cycle row to column time and pre-charge time by locally isolating the digit lines from the N-sense and P-sense amplifier circuits and pre-charging the isolated digit lines is disclosed. A local isolation device is provided between the N-sense amplifier and the digit lines of a memory array. Similarly, a local isolation device is provided between the P-sense amplifier and the digit lines of the memory array. The local isolation devices are controlled by the inversion phase of the column select signal. Additionally, a local pre-charge circuit is provided to pre-charge the isolated digit lines to a voltage potential, such as for example Vcc. The local isolation and pre-charging of the digit lines provides for a faster write cycle, faster pre-charge time and faster row to column time.

Abstract: A column latch device uses first and second latches, the first controlling input to the second, to enable a column line in a redundant column line control system for a memory device. A column select signal is selectively passed to the second latch when the first latch receives a predetermined signal from an address comparator which checks an incoming column address against stored defective addresses.

Abstract: An equilibration circuit for a memory device that prevents excessive current from being drawn by the memory device when a row to column short exists while still allowing the use of segmented column repair is disclosed. Each equilibration circuit of a memory device is connected to the equilibration voltage through a transistor that is controlled by a pulsed signal. When the pulsed signal is high, the transistor will turn on, connecting the digital lines to the equilibration voltage to pre-charge the digit lines to the equilibration voltage. The pulse duration is short enough, however, to turn the transistor off before the equilibration voltage can be pulled down if a column to row short exists.

Abstract: A column latch device uses first and second latches, the first controlling input to the second, to enable a column line in a redundant column line control system for a memory device. A column select signal is selectively passed to the second latch when the first latch receives a predetermined signal from an address comparator which checks an incoming column address against stored defective addresses.

Abstract: An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops and active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal.

Abstract: A method and apparatus for reading or strobing antifuse circuits in a memory device is described. A read signal, also called a strobe signal, is generated from a circuit which includes a model antifuse similar to antifuses employed in the antifuse circuits. The read signal is a single pulse having a duration determined by an amount of time needed to charge the model antifuse such that the read signal is long enough to be applied to properly read antifuse circuits in the memory device. A reset pulse may be generated having a duration determined by the amount of time needed to charge the model antifuse, and the reset pulse may be applied to initialize registers in the memory device and to generate the read signal.

Abstract: An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal.

Abstract: An SDRAM is initialized with an initialization pulse generated in response to a load mode register command that is generated to program a mode register in the SDRAM. Antifuse circuits are read and registers are initialized according to the initialization pulse each time the mode register is programmed. The mode register is programmed in a boot up procedure and in subsequent reboot procedures of a computer system including the SDRAM.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: A method and apparatus for reading or strobing antifuse circuits in a memory device is described. A read signal, also called a strobe signal, is generated from a circuit which includes a model antifuse similar to antifuses employed in the antifuse circuits. The read signal is a single pulse having a duration determined by an amount of time needed to charge the model antifuse such that the read signal is long enough to be applied to properly read antifuse circuits in the memory device. A reset pulse may be generated having a duration determined by the amount of time needed to charge the model antifuse, and the reset pulse may be applied to initialize registers in the memory device and to generate the read signal.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: A method and apparatus for reading or strobing antifuse circuits in a memory device is described. A read signal, also called a strobe signal, is generated from a circuit which includes a model antifuse similar to antifuses employed in the antifuse circuits. The read signal is a single pulse having a duration determined by an amount of time needed to charge the model antifuse such that the read signal is long enough to be applied to properly read antifuse circuits in the memory device. A reset pulse may be generated having a duration determined by the amount of time needed to charge the model antifuse, and the reset pulse may be applied to initialize registers in the memory device and to generate the read signal.

Abstract: A delay is introduced into the output path of a synchronous device in response to a rising supply voltage. Specifically, as its supply voltage rises, a synchronous memory device may operate too quickly, particularly data output. To slow the rate at which the memory device outputs data, the clock which controls the data output rate is delayed by an amount correlative to the magnitude of the supply voltage.

Abstract: A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.

Abstract: The present invention is embodied in a method and apparatus which permits the testing of a memory device by utilizing normally unused data write lines to conduct the results of the memory test operations to a memory controller or processor. The data read from a specific memory cell is input into a comparator through a data sense amplifier and compared to the data from another memory cell. When the data is not coincident, a switch is enabled causing a data write line to change states. The change of state of the data write line disables a buffer, causing it to output a tri-state signal. A controller detects and interprets the tri-state signal output from the buffer as improper memory functioning.

Abstract: A unique latch circuitry having both a latching and margin testing capability is provided. Every antifuse in a memory circuit is connected to a respective latch circuit. The latch circuits utilize a global input signal to configure a reference impedance with either a normal operational mode impedance or a test mode impedance. Once configured, and without any other additional circuitry, the latch circuits are capable of performing the latching or testing capability based upon comparisons to the reference impedance. When configured for the normal operational mode, the latch circuits read and output the status of their respective antifuses responsive to a control signal. When configured for the testing mode, the latch circuits test the impedance margin of their respective antifuses responsive to the same control signal.

Abstract: A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.

Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

Abstract: A programmable bandwidth I/O port using a DRAM connected to a plurality of serial access memories. Data is synchronously transferred between the DRAM and the serial access memories and is asynchronously transferred between the serial access memories and a plurality of single or multiple bit I/O ports. The bus widths of the I/O ports may be easily programmed to provide a wide variety of I/O port configurations.

Abstract: A system has multiple subsystems and a test signal source resident upon a common substrate. A first subsystem interfaces with an off-substrate functional tester during a test. The test signal source generates a first signal during the test for input to the second subsystem. The second subsystem responds performing an operation independent of operation and current state of the first subsystem. The functional tester verifies the independent operation of the first and second subsystems.