Patents by Inventor Charles L. Reynolds
Charles L. Reynolds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220308564Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Kirk D. Peterson, Steven Paul Ostrander, Stephanie E Allard, Charles L. Reynolds, Sungjun Chun, Daniel M. Dreps, Brian W. Quinlan, Sylvain Pharand, Jon Alfred Casey, David Edward Turnbull, Pascale Gagnon, Jean Labonte, Jean-Francois Bachand, Denis Blanchard
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Patent number: 11388821Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: GrantFiled: April 17, 2020Date of Patent: July 12, 2022Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10892249Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: GrantFiled: May 31, 2019Date of Patent: January 12, 2021Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Patent number: 10840214Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.Type: GrantFiled: August 21, 2019Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Patent number: 10813215Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: GrantFiled: March 14, 2016Date of Patent: October 20, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, KYOCERA CIRCUIT SOLUTIONS INC.Inventors: Jean Audet, Edmund D. Blackshear, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada
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Patent number: 10806030Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: GrantFiled: January 15, 2015Date of Patent: October 13, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, KYOCERA CIRCUIT SOLUTIONS INC.Inventors: Jean Audet, Edmund D. Blackshear, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada
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Patent number: 10756031Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.Type: GrantFiled: May 10, 2019Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Franklin M. Baez, Brian W. Quinlan, Charles L. Reynolds, Krishna R. Tunga, Thomas Weiss
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Publication number: 20200245466Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Inventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10687420Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: GrantFiled: March 14, 2016Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Edmund D. Blackshear, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada
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Patent number: 10679931Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.Type: GrantFiled: March 31, 2019Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
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Patent number: 10660209Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: GrantFiled: November 14, 2017Date of Patent: May 19, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10622299Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.Type: GrantFiled: February 7, 2019Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10515929Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: GrantFiled: April 9, 2018Date of Patent: December 24, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190378816Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190312011Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: ApplicationFiled: May 31, 2019Publication date: October 10, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190312009Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190312010Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Patent number: 10431563Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.Type: GrantFiled: April 9, 2018Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
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Publication number: 20190229045Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.Type: ApplicationFiled: March 31, 2019Publication date: July 25, 2019Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
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Publication number: 20190172784Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.Type: ApplicationFiled: February 7, 2019Publication date: June 6, 2019Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof