Patents by Inventor Charles L. Reynolds
Charles L. Reynolds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190150287Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Inventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10249559Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.Type: GrantFiled: January 18, 2016Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
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Patent number: 10224273Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: October 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10224274Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: October 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20180068945Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: ApplicationFiled: October 28, 2017Publication date: March 8, 2018Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20180053717Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: ApplicationFiled: October 28, 2017Publication date: February 22, 2018Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 9899313Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: July 11, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20180012838Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc. includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20160211229Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: ApplicationFiled: March 14, 2016Publication date: July 21, 2016Applicant: Kyocera Circuit Solutions Inc.Inventors: Jean AUDET, Edmund D. BLACKSHEAR, Masahiro FUKUI, Charles L. REYNOLDS, Kenji TERADA, Tomoyuki YAMADA
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Publication number: 20160210398Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: ApplicationFiled: March 14, 2016Publication date: July 21, 2016Applicant: Kyocera Circuit Solutions Inc.Inventors: Jean AUDET, Edmund D. BLACKSHEAR, Masahiro FUKUI, Charles L. REYNOLDS, Kenji TERADA, Tomoyuki YAMADA
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Publication number: 20160211481Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: ApplicationFiled: January 15, 2015Publication date: July 21, 2016Applicant: KYOCERA CIRCUIT SOLUTIONS INC.Inventors: Jean AUDET, Edmund D. BLACKSHEAR, Masahiro FUKUI, Charles L. REYNOLDS, Kenji TERADA, Tomoyuki YAMADA
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Publication number: 20160133554Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.Type: ApplicationFiled: January 18, 2016Publication date: May 12, 2016Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
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Patent number: 9263378Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.Type: GrantFiled: August 4, 2014Date of Patent: February 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
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Publication number: 20160035659Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.Type: ApplicationFiled: August 4, 2014Publication date: February 4, 2016Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
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Patent number: 8680670Abstract: A multi-chip module (MCM) includes chip sub-modules that are fabricated as self-contained testable entities. The chip sub-modules plug into respective sockets in a frame of the MCM. Each chip sub-module may be tested before being plugged into the MCM. A chip sub-module may include an IC chip, such as a processor, mounted to an sub-module organic substrate that provides interconnects to the chip. The frame into which each chip sub-module plugs sits on a mini-card organic substrate that interconnects the chip sub-modules together. The MCM may include a downstop between the mini-card organic substrate and a system board to limit or prevent solder creep of solder connections between the mini-card organic substrate and the system board.Type: GrantFiled: October 22, 2010Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Jon Alfred Casey, John Lee Colbert, Paul Marian Harvey, Mark Kenneth Hoffmeyer, Charles L Reynolds
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Publication number: 20120098116Abstract: A multi-chip module (MCM) includes chip sub-modules that are fabricated as self-contained testable entities. The chip sub-modules plug into respective sockets in a frame of the MCM. Each chip sub-module may be tested before being plugged into the MCM. A chip sub-module may include an IC chip, such as a processor, mounted to an sub-module organic substrate that provides interconnects to the chip. The frame into which each chip sub-module plugs sits on a mini-card organic substrate that interconnects the chip sub-modules together. The MCM may include a downstop between the mini-card organic substrate and a system board to limit or prevent solder creep of solder connections between the mini-card organic substrate and the system board.Type: ApplicationFiled: October 22, 2010Publication date: April 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jon Alfred Casey, John Lee Colbert, Paul Marlan Harvey, Mark Kenneth Hoffmeyer, Charles L. Reynolds
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Patent number: 7932342Abstract: A method to reduce liquid polymer macromolecule mobility through forming a polymer blend system is provided. More particularly, a small amount of polymer crosslinker is added to a liquid polymer matrix to prevent intermolecular movement. The crosslinker functions as cages to block linear or branched linear macromolecules and prevent them from sliding into each other.Type: GrantFiled: January 16, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Steven E Molis, Charles L Reynolds, William E Sablinski, Jiali Wu
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Patent number: 7808099Abstract: A liquid thermal interface (LTI) including a mixture of a linearly structured polymer doped with crosslinked networks and related method are presented. The LTI exhibits reduced liquid polymer macromolecule mobility, and thus increased surface tension. An embodiment of the method includes mixing a crosslinker with a linearly structured polymer to form a mixture, wherein the crosslinker includes a base agent including a vinyl-terminated or branched polydimethylsiloxane, and a curing agent including a hydrogen-terminated polydimethylsiloxane; and curing the mixture. The crosslinker functions as cages to block linear or branched linear macromolecules and prevents them from sliding into each other, thus increasing surface tension of the resulting LTI.Type: GrantFiled: May 6, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Randall J. Bertrand, Mark S. Chace, David L. Gardell, George J. Lawson, Yvonne Morris, Charles L. Reynolds, Jiali Wu
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Publication number: 20090281254Abstract: A liquid thermal interface (LTI) including a mixture of a linearly structured polymer doped with crosslinked networks and related method are presented. The LTI exhibits reduced liquid polymer macromolecule mobility, and thus increased surface tension. An embodiment of the method includes mixing a crosslinker with a linearly structured polymer to form a mixture, wherein the crosslinker includes a base agent including a vinyl-terminated or branched polydimethylsiloxane, and a curing agent including a hydrogen-terminated polydimethylsiloxane; and curing the mixture. The crosslinker functions as cages to block linear or branched linear macromolecules and prevents them from sliding into each other, thus increasing surface tension of the resulting LTI.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Randall J. Bertrand, Mark S. Chace, David L. Gardell, George J. Lawson, Yvonne Morris, Charles L. Reynolds, Jiali Wu
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Publication number: 20090182161Abstract: A method to reduce liquid polymer macromolecule mobility through forming a polymer blend system is provided. More particularly, a small amount of polymer crosslinker is added to a liquid polymer matrix to prevent intermolecular movement. The crosslinker functions as cages to block linear or branched linear macromolecules and prevent them from sliding into each other.Type: ApplicationFiled: January 16, 2008Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven E. MOLIS, Charles L. REYNOLDS, William E. SABLINSKI, Jiali WU