Abstract: A magnetic read head with reduced side reading characteristics is described. This design combines use of a current channeling layer (CCL) with stabilizing longitudinal bias layers whose magnetization direction is canted relative to that of the free layer easy axis and that of the pinned layer (of the GMR). This provides several advantages: First, the canting of the free layer at the side region results in a reduction of side reading by reducing magnetic sensitivity in that region. Second, the CCL leads to a narrow current flow profile at the side region, therefore producing a narrow track width definition. A process for making this device is described. Said process allows some of the requirements for interface cleaning associated with prior art processes to be relaxed.

Abstract: Methods of forming electrostatically charged gelatin are provided. Gelatin is extracted by an acid extraction method (12) thereby producing a gelatin dispersion (14), the pH of which is adjusted to the isoelectric point of the gelatin. The pH of the gelatin dispersion (14) is then further adjusted (22) so as to cause the gelatin to assume an electrostatic charge.

Abstract: A magnetic read head with reduced side reading characteristics is described. This design combines use of a current channeling layer (CCL) with stabilizing longitudinal bias layers whose magnetization direction is canted relative to that of the free layer easy axis and that of the pinned layer (of the GMR). This provides several advantages: First, the canting of the free layer at the side region results in a reduction of side reading by reducing magnetic sensitivity in that region. Second, the CCL leads to a narrow current flow profile at the side region, therefore producing a narrow track width definition. A process for making this device is described. Said process allows some of the requirements for interface cleaning associated with prior art processes to be relaxed.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract: Methods of forming electrostatically charged gelatin are provided. Gelatin is extracted by an acid extraction method (12) thereby producing a gelatin dispersion (14), the pH of which is adjusted to the isoelectric point of the gelatin. The pH of the gelatin dispersion (14) is then further adjusted (22) so as to cause the gelatin to assume an electrostatic charge.

Abstract: Animal feed compositions comprising amounts of protein, carbohydrate, fat and a functional ingredient for preventing hairball formation are provided. The functional ingredient comprises an electrostatically charge ingredient, preferably selected from the group consisting of electrostatically charged proteins, amino acids, conjugated proteins, dipeptides, multipeptides, protein colloids, enzymes, protein hydrolysates, natural and artificial food additives, flavorings, seasonings, and mixtures thereof.

Abstract: Animal feed compositions comprising amounts of protein, carbohydrate, fat and a functional ingredient for preventing hairball formation are provided.

Abstract: A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Abstract: A magnetic read head with reduced side reading characteristics is described. This design combines use of a current channeling layer (CCL) with stabilizing longitudinal bias layers whose magnetization direction is canted relative to that of the free layer easy axis and that of the pinned layer (of the GMR). This provides several advantages: First, the canting of the free layer at the side region results in a reduction of side reading by reducing magnetic sensitivity in that region. Second, the CCL leads to a narrow current flow profile at the side region, therefore producing a narrow track width definition. A process for making this device is described. Said process allows some of the requirements for interface cleaning associated with prior art processes to be relaxed.

Abstract: A method for increasing radiosensitivity of a tumor in a subject via administration of a VEGF-R2 inhibitor to a tumor in a subject. Also provided are methods for delaying tumor growth and for inhibiting tumor blood vessel growth via administration of a VEGF-R2 inhibitor.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract: A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titanium layer, where the titanium layer contacts the electrode contact region of the silicon substrate layer. There is then processed thermally the titanium layer in a nitrogen containing atmosphere to form a titanium silicide layer in contact with the electrode contact region and a titanium nitride layer formed thereover, where the titanium layer is completely consumed in forming the titanium silicide layer and the titanium nitride layer. Finally, there is formed upon the titanium nitride layer a barrier layer.

Abstract: An improved read-write head for use with magnetic disks is described. This improvement has been achieved by providing the read head with shields that are limited to performing only shielding and do not share other magnetic functions with parts of the write head. This allows the write pole to be located very close to the read head since the top shield is no longer required to provide a flux return path, this function now being provided by a separate return flux pole. The separation between the read and write heads is now limited only by the need to achieve an optimum vertical field profile. Two key advantages of this structure are a substantial reduction in the jagging distance of the system and a reduced interference field from the write flux.

Abstract: In one embodiment, a semiconductor substrate (38) is uniformly polished using a polishing pad (16) that has a first polishing region (26), a second polishing region (28), and a third polishing region (30). The semiconductor substrate (38) is aligned to the polishing pad (16), such that the center of the semiconductor substrate (38) overlies the second polishing region (28), and the edge of the semiconductor substrate overlies the first polishing region (26) and the third polishing region (30). During polishing, the semiconductor substrate (38) is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate (38). This allows the semiconductor substrate (38) to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate (38) are not over polished.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract: In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.

Abstract: It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing method for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered “hard mask” on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal.

Abstract: An improved and new substrate carrier head for use in a CMP apparatus is described. The new substrate carrier head has a substrate retaining ring with embedded intersecting channels in the outer face. The embedded intersecting channels improve the circulation of polishing slurry to and from the polished substrate and polishing byproducts away from the polished substrate and thereby improve the polishing uniformity on the substrate.

Abstract: A method for depositing silicon dioxide between features has been achieved. The method may be applied intermetal dielectrics, interlevel dielectric, or shallow trench isolations. This method prevents dielectric voids, corner clipping, and plasma induced damage in very small feature applications. Features, such as conductive traces, are provided overlying a semiconductor substrate where the spaces between the features form gaps. A silicon dioxide liner layer is deposited overlying the features and lining the gaps, yet leaving the gaps open. The silicon dioxide liner layer depositing step is by high density plasma, chemical vapor deposition (HDP CVD) using a gas mixture comprising silane, oxygen, and argon. The argon gas pressure, chamber pressure, and the sputter rf energy are kept low. A silicon dioxide gap filling layer is deposited overlying the silicon dioxide liner layer to fill the gaps, and the integrated circuit device is completed.