Abstract: One aspect of the invention is a method for restricting access to one or more email attachments includes receiving an email addressed to a first recipient and including at least a first attachment. The email is processed to determine whether a valid authorization code is associated with the email (and/or the attachment (s)). The valid authorization code identifies the email (and/or the attachment(s)) as an authorized communication. Access by the recipient to the first attachment is prevented if the processing of the email determined that no valid authorization code is associated with the email (and/or the attachment(s)).

Abstract: A leak detection material and method of introducing the leak detection material into a fluid system such as a climate control system, an engine oil system, or a fuel system is described. The leak detection material can be a dye delivery composition including a mixture of leak detection dye and a solid carrier.

Abstract: The matched nodes provide protection for a failure in the connection between two bidirectional line switched rings. They use a secondary path in case of a primary path failure. The secondary path is set aside in either the working or protection bandwidth of the rings, thus wasting resources. The invention uses a dedicated secondary path between the primary and secondary nodes. With the invention, no ring protection mechanisms are compromised and the ring bandwidth is not wasted. Middle nodes also realize full add/drop capabilities.

Abstract: The matched nodes provide protection for a failure in the connection between two bidirectional line switched rings. They use a secondary path in case of a primary path failure. The secondary path is set aside in either the working or protection bandwidth of the rings, thus wasting resources. The invention uses inter-ring protection mechanisms which do away with a specifically set aside secondary path between the primary and secondary nodes.

Abstract: An electrochemical electrode of a tube of porous titanium suboxide with a contact connection to an electrical supply.

Abstract: A field programmable gate array (FPGA) comprising a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM is disclosed. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of "AND" gates and an array of "OR" gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

Abstract: An image processing system 20 comprises a format converter 21 for receiving a first signal having a larger bandwidth and a second signal having a smaller bandwidth, the first and second signals together representing an image. A processor 23 is arranged to process the first and second signals to produce signals representing a manipulated version of the image. The system further comprises a deriving circuit 25 which is arranged to derive from information in the larger bandwidth signal additional information for the smaller bandwidth signal. The deriving circuit derives an unknown value of a pixel as represented by the smaller bandwidth signal from known values of the pixel and the pixels adjacent thereto as represented by the larger bandwidth signal and from known values of the adjacent pixels as represented by the smaller bandwidth signal. The deriving circuit facilitates conversion of the first and second signals into another signal format representing the image.

Abstract: A field programmable gate array (FPGA) includes a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of "AND" gates and an array of "OR" gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

Abstract: A mounting and housing is provided for the electrode terminal of a neon tube and the electrical conduit extending therefrom. Such housing comprises a pair of walls formed of a shapable insulating material and held in spaced relationship to each other by a base secured to the wall or ceiling surface upon which the housing is to be mounted. The walls define a first cavity which encompasses the neon tube terminal and a second cavity adapted to carry the electrical conduit from the electrode terminal to a transformer or another electrode terminal.

Abstract: A method of manufacturing an electrode which comprises depositing an oxide of titanium from a solution onto a surface of a film-forming metal, heating the oxide to dry it, depositing a second titanium oxide layer on the first oxide layer and then depositing an electrocatalytic layer onto the titanium oxide layers.