Patents by Inventor Charles W. Eichelberger

Charles W. Eichelberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8590145
    Abstract: Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: November 26, 2013
    Assignee: Epic Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 8564119
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: October 22, 2013
    Assignee: Epic Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 8533941
    Abstract: A method of bonding two structures together with an adhesive line of controlled thickness is provided. The method includes: applying an adhesive of controlled thickness to a first surface of a first structure; at least partially curing the adhesive; applying additional adhesive to the partially cured adhesive applied to the first surface or to a second surface of a second structure; holding the first structure and the second structure in alignment with the first surface and the second surface disposed in spaced, opposing relation; applying a force to the first structure and/or the second structure to squeeze the additional adhesive between the second surface and the partially cured adhesive applied to the first surface to reduce a thickness of the additional adhesive; and at least partially curing the additional adhesive to bond the first and second structures together.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: September 17, 2013
    Assignee: Epic Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 8474133
    Abstract: Methods of fabricating a base layer circuit structure are provided. One fabrication method includes: providing an alignment carrier having a support surface; forming a plurality of electrically conductive structures above the support surface of the alignment carrier; disposing a structural material around and physically contacting the side surfaces of the electrically conductive structures formed above the support surface, the structural material having an upper surface coplanar with or parallel to the upper surface of one or more of the electrically conductive structures; exposing, if covered, the upper surfaces of the electrically conductive structures to facilitate electrical connection to the structures; and separating the alignment carrier from the base layer circuit structure. The base layer circuit structure includes the plurality of electrically conductive structures and the structural material surrounding and physically contacting the electrically conductive structures.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: July 2, 2013
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 8384199
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 26, 2013
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 8324020
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 4, 2012
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 8169065
    Abstract: Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: May 1, 2012
    Assignee: EPIC Technologies, Inc.
    Inventors: James E. Kohl, Charles W. Eichelberger
  • Publication number: 20110147911
    Abstract: Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Applicant: EPIC Technologies, Inc.
    Inventors: James E. Kohl, Charles W. Eichelberger
  • Patent number: 7868445
    Abstract: Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 11, 2011
    Assignee: EPIC Technologies, Inc.
    Inventors: James E. Kohl, Charles W. Eichelberger
  • Patent number: 7863090
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 4, 2011
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Patent number: 7830000
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 9, 2010
    Assignee: Epic Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Publication number: 20100047970
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Application
    Filed: November 3, 2009
    Publication date: February 25, 2010
    Applicant: EPIC Technologies, Inc.
    Inventors: Charles W. EICHELBERGER, James E. KOHL
  • Publication number: 20100044855
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Application
    Filed: November 3, 2009
    Publication date: February 25, 2010
    Applicant: EPIC TECHNOLOGIES, INC.
    Inventors: Charles W. EICHELBERGER, James E. KOHL
  • Publication number: 20100032091
    Abstract: A method of bonding two structures together with an adhesive line of controlled thickness is provided. The method includes: applying an adhesive of controlled thickness to a first surface of a first structure; at least partially curing the adhesive; applying additional adhesive to the partially cured adhesive applied to the first surface or to a second surface of a second structure; holding the first structure and the second structure in alignment with the first surface and the second surface disposed in spaced, opposing relation; applying a force to the first structure and/or the second structure to squeeze the additional adhesive between the second surface and the partially cured adhesive applied to the first surface to reduce a thickness of the additional adhesive; and at least partially curing the additional adhesive to bond the first and second structures together.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 11, 2010
    Applicant: EPIC TECHNOLOGIES, INC.
    Inventors: Charles W. EICHELBERGER, James E. KOHL
  • Publication number: 20100031500
    Abstract: Methods of fabricating a base layer circuit structure are provided. One fabrication method includes: providing an alignment carrier having a support surface; forming a plurality of electrically conductive structures above the support surface of the alignment carrier; disposing a structural material around and physically contacting the side surfaces of the electrically conductive structures formed above the support surface, the structural material having an upper surface coplanar with or parallel to the upper surface of one or more of the electrically conductive structures; exposing, if covered, the upper surfaces of the electrically conductive structures to facilitate electrical connection to the structures; and separating the alignment carrier from the base layer circuit structure. The base layer circuit structure includes the plurality of electrically conductive structures and the structural material surrounding and physically contacting the electrically conductive structures.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 11, 2010
    Applicant: EPIC TECHNOLOGIES, INC.
    Inventors: Charles W. EICHELBERGER, James E. KOHL
  • Publication number: 20100035384
    Abstract: Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 11, 2010
    Applicant: EPIC TECHNOLOGIES, INC.
    Inventors: Charles W. EICHELBERGER, James E. KOHL
  • Patent number: 7619901
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 17, 2009
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl
  • Publication number: 20080315391
    Abstract: Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 25, 2008
    Applicant: EPIC Technologies, Inc.
    Inventors: James E. Kohl, Charles W. Eichelberger
  • Publication number: 20080315404
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 25, 2008
    Applicant: EPIC TECHNOLOGIES, INC.
    Inventors: Charles W. EICHELBERGER, James E. KOHL
  • Publication number: 20080315375
    Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 25, 2008
    Applicant: EPIC TECHNOLOGIES, INC.
    Inventors: Charles W. EICHELBERGER, James E. KOHL