Abstract: Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

Abstract: A molded equipment pad having a top deck, side walls, underlying reinforcing radial ribs, and underlying reinforcing arc-shaped ribs. The arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad and that extend toward the side walls of the pad and a number of distributed circular hubs. Alternatively, the arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad that end short of the side walls, a series of opposing arc-shaped ribs that are centered on the corners of the equipment pad, and a number of distributed circular hubs.

Abstract: A molded equipment pad having a top deck, side walls, underlying reinforcing radial ribs, and underlying reinforcing arc-shaped ribs. The arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad and that extend toward the side walls of the pad and a number of distributed circular hubs. Alternatively, the arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad that end short of the side walls, a series of opposing arc-shaped ribs that are centered on the corners of the equipment pad, and a number of distributed circular hubs.

Abstract: A molded equipment pad having a top deck, side walls, underlying reinforcing radial ribs, and underlying reinforcing arc-shaped ribs. The arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad and that extend toward the side walls of the pad and a number of distributed circular hubs. Alternatively, the arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad that end short of the side walls, a series of opposing arc-shaped ribs that are centered on the corners of the equipment pad, and a number of distributed circular hubs.

Abstract: Examples are provided that relate to determining a capacitance based on a charge accumulated on a sense capacitor electrode. One example provides a head-mounted device comprising a facial-tracking sensor, a controller, and a charge sensing circuit connected to the facial-tracking sensor. The facial-tracking sensor includes a sense capacitor electrode configured to be positioned proximate to a surface of a face and form a capacitance based upon a distance between the sense capacitor electrode and the surface of the face, and the controller configured to apply a reference voltage to the sense capacitor electrode. The charge sensing circuit is configured to determine the capacitance of the sense capacitor electrode by determining an amount of charge accumulated on the sense capacitor electrode resulting from the reference voltage.

Abstract: Systems and methods for isolating faults in die-to-die interconnects are provided. A method includes providing a first transmission path, along a die-to-die interconnect, from a transmitter associated with a first die to an asynchronous buffer associated with a second die. The method further includes providing a second transmission path from voltage reference circuitry associated with the second die to the asynchronous buffer associated with the second die. The method further includes simultaneously enabling both the first transmission path and the second transmission path to allow the asynchronous buffer to receive inputs from both the transmitter associated with the first die and the voltage reference circuitry associated with the second die, such that the inputs received by the asynchronous buffer are indicative of: (1) no failure in the die-to-die interconnect, (2) an open failure in the die-to-die interconnect, or (3) a short failure in the die-to-die interconnect.

Abstract: A request associated with accessing resources of the second party may be received at a first agent installed on a device for a first party, the being received from a second agent installed on the device for a second party. Based on the request, a signed access request that includes a refresh token previously obtained from a service of the resource management system (RMS) may be sent to the service of the RMS. The signed access request may be signed by a private key of the device. Also, a public key of the device corresponding to the private key may be registered with the service of the RMS. In response to sending the signed access request, a session token associated with accessing the resources of the second through the second agent may be received by the first agent from the service of the RMS.

Abstract: A computing device, such as a server, has a sealed housing and runs one or more data extraction agents. In some embodiments, the computing device includes one or more processors and memory located inside the sealed housing, the memory stores instructions that when executed by the one or more processors causes the one or more processors to: authenticate with a data recipient system using a prestored security engine and using a shared registration secret uniquely associating the computing device with the data recipient system; retrieve an extraction job specification from an extraction job specification repository associated with the data recipient system; and using the extraction job specification, communicate to one or more client computing devices associated with a client system to extract data records from one or more data stores of the client system. Related methods are also disclosed.

Abstract: A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.

Abstract: A molded equipment pad having a top deck, side walls, underlying reinforcing radial ribs, and underlying reinforcing arc-shaped ribs. The arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad and that extend toward the side walls of the pad and a number of distributed circular hubs. Alternatively, the arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad that end short of the side walls, a series of opposing arc-shaped ribs that are centered on the corners of the equipment pad, and a number of distributed circular hubs.

Abstract: A computing device, such as a server, has a sealed housing and runs one or more data extraction agents. In some embodiments, the computing device includes one or more processors and memory located inside the sealed housing, the memory stores instructions that when executed by the one or more processors causes the one or more processors to: authenticate with a data recipient system using a prestored security engine and using a shared registration secret uniquely associating the computing device with the data recipient system; retrieve an extraction job specification from an extraction job specification repository associated with the data recipient system; and using the extraction job specification, communicate to one or more client computing devices associated with a client system to extract data records from one or more data stores of the client system. Related methods are also disclosed.

Abstract: Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

Abstract: A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.

Abstract: Examples are disclosed that relate to determining a capacitance based on a charge accumulated on a sense capacitor electrode. One example provides a head-mounted device comprising a facial-tracking sensor, a controller, and a charge sensing circuit connected to the facial-tracking sensor. The facial-tracking sensor comprises a sense capacitor electrode configured to be positioned proximate to a surface of a face and form a capacitance based upon a distance between the sense capacitor electrode and the surface of the face, and the controller configured to apply a reference voltage to the sense capacitor electrode. The charge sensing circuit is configured to determine the capacitance of the sense capacitor electrode by determining an amount of charge accumulated on the sense capacitor electrode resulting from the reference voltage.

Abstract: A molded equipment pad having a top deck, side walls, underlying reinforcing radial ribs, and underlying reinforcing arc-shaped ribs. The arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad and that extend toward the side walls of the pad and a number of distributed circular hubs. Alternatively, the arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad that end short of the side walls, a series of opposing arc-shaped ribs that are centered on the corners of the equipment pad, and a number of distributed circular hubs.

Abstract: A molded equipment pad having a top deck, side walls, underlying reinforcing radial ribs, and underlying reinforcing arc-shaped ribs. The arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad and that extend toward the side walls of the pad and a number of distributed circular hubs. Alternatively, the arc-shaped ribs may include a series of concentric arc-shaped ribs that are centered on the center of the equipment pad that end short of the side walls, a series of opposing arc-shaped ribs that are centered on the corners of the equipment pad, and a number of distributed circular hubs.

Abstract: A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.

Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.

Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.

Abstract: A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.