Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract: Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.

Abstract: Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract: Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.

Abstract: Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least two sublayers of oriented carbon nanotubes. A first sublayer is created by growing carbon nanotubes in a first direction parallel to the chip substrate from a catalyst in the presence of a reactant gas flow in the first direction, and a second sublayer is created by growing carbon nanotubes in a second direction parallel to the substrate and different from the first direction from a catalyst in the presence of a reactant gas flow in the second direction. The first and second directions are preferably substantially perpendicular. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal.

Abstract: A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

Abstract: A structure and a method for forming the same. The method includes providing a structure which includes (a) a to-be-patterned layer, (b) a photoresist layer on top of the to-be-patterned layer wherein the photoresist layer includes a first opening, and (c) a cap region on side walls of the first opening. A first top surface of the to-be-patterned layer is exposed to a surrounding ambient through the first opening. The method further includes performing a first lithography process resulting in a second opening in the photoresist layer. The second opening is different from the first opening. A second top surface of the to-be-patterned layer is exposed to a surrounding ambient through the second opening.

Abstract: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.

Abstract: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

Abstract: Methods for synthesizing carbon nanotubes and structures formed thereby, includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access.

Abstract: Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.