Abstract: A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

Abstract: Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

Abstract: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

Abstract: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

Abstract: An apparatus for immersion optical lithography having a lens capable of relative movement in synchrony with a horizontal motion of a semiconductor wafer in a liquid environment where the synchronous motion of the lens apparatus and semiconductor wafer advantageously reduces the turbulence and air bubbles associated with a liquid environment. The relative motions of the lens and semiconductor wafer are substantially the same as the scanning process occurs resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption of the liquid environment.

Abstract: Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.

Abstract: A photolithographic apparatus, system and method employing an improved refractive medium. The photolithographic apparatus may be used in an immersion lithography system for projecting light onto a workpiece such as a semiconductor wafer. In one embodiment, the photolithographic apparatus includes a container containing a transparent fluid. The fluid container is positioned between a lens element and the wafer. The container is further characterized as having a substantially flexible and transparent bottom membrane contacting an upper surface of the wafer and overlapping at least one side edge of the wafer such that a fluid filled skirt is formed extending beyond the edges of the wafer.

Abstract: A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.

Abstract: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.

Abstract: A method is provided for forming a quadruple density sidewall image transfer (SIT) structure. Oxide spacers are formed on opposite sidewalls of a first mandrel. The oxide spacers form a second mandrel. Then sidewall spacers are formed on opposite sidewalls of the oxide spacers forming the second mandrel. A pattern of the sidewall spacers is used to form the quadruple density sidewall image transfer (SIT) structure. The method of the invention enables formation of four well-controlled lines for each lithographically minimum pitch dimension.

Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.

Abstract: A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features characteristic of the damascene process are formed by standard lithographic and etch processes in the mandrel material for each level of the interconnect structure. The conductive features in each level are surrounded by the mandrel material. After all levels of the interconnect structure are formed, a passageway is provided to the mandrel material. An isotropic etchant is introduced through the passageway that selectively etches and removes the mandrel material. The spaces formerly occupied by the mandrel material in the levels of the interconnect structure are filled by air, which operates as a low-k dielectric material.

Abstract: A semiconductor device having low-leakage borderless contacts is formed by etching contact openings adjacent first and second electronic elements of opposite dopant type, conformally depositing a thin doped polysilicon layer, protecting the electronic element of similar dopant-type, removing the thin doped polysilicon layer adjacent the oppositely doped electronic element diffusing dopant from said polysilicon layer into a side wall of the electronic element of similar dopant-type, and then depositing tungsten within the contact openings.