Patents by Inventor Chau Fatt Chiang

Chau Fatt Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791169
    Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 17, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Pei Luan Pok, Roslie Saini bin Bakar, Chau Fatt Chiang, Chee Hong Lee, Swee Kah Lee, Yu Shien Leong, Jan Sing Loh, Yean Seng Ng
  • Publication number: 20230178428
    Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Thorsten Meyer, Fee Hoon Wendy Wong, Thomas Behrens, Eric Lopez Bonifacio, Chau Fatt Chiang, Irmgard Escher-Poeppel, Giovanni Ragasa Garbin, Martin Gruber, Tien Shyang Law, Mohamad Azian Mohamed Azizi, Si Hao Vincent Yeo
  • Publication number: 20230170329
    Abstract: A method of forming a semiconductor package includes providing a metal baseplate including a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.
    Type: Application
    Filed: August 16, 2022
    Publication date: June 1, 2023
    Inventors: Sock Chien Tey, Keck Tim Ang, Chan Lam Cha, Chau Fatt Chiang, Badrul Hisyam Ismail, Desmond Jenn Yong Loo, Ronizan Mohd Salleh, Norliza Morban, Si Hao Vincent Yeo, Chee Mun Wai, Fee Hoon Wendy Wong
  • Publication number: 20230170226
    Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Chau Fatt Chiang, Thorsten Meyer, Chan Lam Cha, Wern Ken Daryl Wee, Chee Hong Lee, Swee Kah Lee, Norliza Morban, Khay Chwan Andrew Saw
  • Patent number: 11587800
    Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 21, 2023
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Khay Chwan Andrew Saw, Chee Voon Tan
  • Publication number: 20230049564
    Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices each of the sidewall-facing terminals is electrically connected to the semiconductor die of the respective packaged semiconductor device.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Inventors: Chau Fatt Chiang, Khay Chwan Andrew Saw, Chee Voon Tan
  • Patent number: 11569196
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: January 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Publication number: 20220278085
    Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.
    Type: Application
    Filed: February 22, 2022
    Publication date: September 1, 2022
    Applicant: Infineon Technologies AG
    Inventors: Chau Fatt CHIANG, Paul Armand Asentista CALO, Chan Lam CHA, Kok Yau CHUA, Chee Hong LEE, Swee Kah LEE, Theng Chao LONG, Jayaganasan NARAYANASAMY, Khay Chwan Andrew SAW
  • Publication number: 20220199478
    Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Inventors: Si Hao Vincent Yeo, Chan Lam Cha, Ying Dieh Cheong, Chau Fatt Chiang, Cher Hau Danny Koh, Wern Ken Daryl Wee, Swee Kah Lee, Desmond Jenn Yong Loo, Fortunato Lopez, Norliza Morban, Khay Chwan Andrew Saw, Sock Chien Tey, Mei Yong Wang
  • Patent number: 11302613
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Patent number: 11274984
    Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 15, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw
  • Publication number: 20220037222
    Abstract: A semiconductor package includes a semiconductor die, an encapsulation encapsulating the semiconductor die, the encapsulation having a first side and an opposing second side, a plurality of contact pads for electrically contacting the semiconductor die, the contact pads being arranged on the first side of the encapsulation, and a plurality of inspection holes arranged in communication with the contact pads and extending from the first side to the second side, such that solder joints on the first side of the encapsulation are optically inspectable using the inspection holes viewed from the second side of the encapsulation.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 3, 2022
    Inventors: Khay Chwan Andrew Saw, Chau Fatt Chiang, Norliza Morban
  • Publication number: 20210391298
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 16, 2021
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Publication number: 20210366732
    Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Chau Fatt Chiang, Khay Chwan Andrew Saw, Chee Voon Tan
  • Patent number: 11174152
    Abstract: An embodiment device includes a body structure having an interior cavity, a control chip disposed on a first interior surface of the interior cavity, and a sensor attached, at a first side, to a second interior surface of the interior cavity opposite the first interior surface. The sensor has a mounting pad on a second side of the sensor that faces the first interior surface, and the sensor is vertically spaced apart from the control chip by an air gap, with the sensor is aligned at least partially over the control chip. The device further includes an interconnect having a first end mounted on the mounting pad, the interconnect extending through the interior cavity toward the first interior surface, and the control chip is in electrical communication with the sensor by way of the interconnect.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 16, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Swee Kah Lee, Chee Yang Ng
  • Publication number: 20210313294
    Abstract: A semiconductor package includes a carrier having a recess, a semiconductor die arranged on the carrier such that a first side of the semiconductor die faces the carrier, and a contact clip arranged over a second side of the semiconductor die, opposite the first side. The contact clip includes a lowered part. The lowered part is arranged in the recess.
    Type: Application
    Filed: March 24, 2021
    Publication date: October 7, 2021
    Inventors: Chau Fatt Chiang, Xavier Arokiasamy, Naveendran Chellamuthu, Chee Chiew Chong, Joo Ming Goa, Chee Hong Lee, Muhammat Sanusi Muhammad, Chee Voon Tan, Wee Boon Tay
  • Patent number: 11133281
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Khay Chwan Saw, Chau Fatt Chiang, Stefan Macheiner, Wae Chet Yong
  • Patent number: 11081417
    Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Soon Lock Goh, Swee Kah Lee, Joachim Mahler, Mei Chin Ng, Beng Keh See, Guan Choon Matthew Nelson Tee
  • Publication number: 20210050227
    Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Inventors: Pei Luan Pok, Roslie Saini bin Bakar, Chau Fatt Chiang, Chee Hong Lee, Swee Kah Lee, Yu Shien Leong, Jan Sing Loh, Yean Seng Ng
  • Publication number: 20210025774
    Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.
    Type: Application
    Filed: June 2, 2020
    Publication date: January 28, 2021
    Inventors: Chau Fatt Chiang, Paul Armand Asentista Calo, Chan Lam Cha, Kok Yau Chua, Jo Ean Chye, Chee Hong Lee, Swee Kah Lee, Theng Chao Long, Jayaganasan Narayanasamy, Khay Chwan Saw