Abstract: A method of forming a semiconductor package includes the following steps. A redistribution layer structure is formed over a first die and a dummy die, wherein the redistribution layer structure is directly electrically connected to the first die. An insulating layer is formed, wherein the insulating layer is disposed opposite to the redistribution layer structure with respect to the first die. At least one thermal through via is formed in the insulating layer.

Abstract: Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.

Abstract: Disclosed herein a friction brake system comprises a braking member connectable to at least one brake pad and configured for pressing the brake pad against a friction surface and a transmission unit configured for converting a rotary motion generated by an actuator into a braking motion of the brake pad wherein the transmission unit comprises a ball-in-ramp assembly having a first plate with at least one groove, a second plate with at least one groove facing the groove of the first plate, and at least one ball arranged between the first plate and the second plate wherein the ball is retained by the groove of the first plate and the groove of the second plate, wherein the ball-in-ramp assembly is configured to convert a rotary motion of the first plate into a translational motion of the second plate relative to the first plate.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

Abstract: Brake system (1) for a vehicle is provided, comprising a first hydraulic circuit (10) including a first wheel brake (11), a second hydraulic circuit (20) including a second wheel brake (21), a first hydraulic pressure supplier (12) including an actuator for pressurizing the first hydraulic circuit (10) in a normal operating mode, a second hydraulic pressure supplier (22) including an actuator for pressurizing the second hydraulic circuit (20) in the normal operating mode, a cut-off valve (30) hydraulically connecting the first and second hydraulic circuits (10, 20), a first control unit (14) for controlling the cut-off valve (30) and activating the first hydraulic pressure supplier (12) and the second hydraulic pressure supplier (22) depending on a brake request, and a second control unit (24) for controlling the cut-off valve (30) and activating the first hydraulic pressure supplier (12) and the second hydraulic pressure supplier (22) depending on a brake request.

Abstract: A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: The present invention relates to a brake system comprising a brake pedal; a master cylinder including a first master chamber, a second master chamber, a first master piston, and a second master piston; a first hydraulic circuit; a second hydraulic circuit; a hydraulic pressure supplier including an actuator for pressurizing the first hydraulic circuit and the second hydraulic circuit depending on an operation of the brake pedal in a normal operating mode of the brake system; and an elastic pedal feel element arranged in the first master chamber to be in contact with the first master piston and the second master piston for generating a pedal force when the brake pedal is operated while the second master piston is locked in the normal operating mode.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.

Abstract: An electronic device is provided and includes a first voltage trace, a second voltage trace, a first region electrode, a second region electrode, and a voltage source module. The second voltage trace is electrically insulated from the first voltage trace, the first region electrode is electrically connected to the first voltage trace, and the second region electrode is electrically connected to the second voltage trace. The voltage source module provides a first driving voltage to the first voltage trace and provides a second driving voltage to the second voltage trace, in which the first driving voltage is different from the second driving voltage. In a top-view direction of the electronic device, the first voltage trace is separated from the second voltage trace, and the first voltage trace and the second voltage trace are formed of a conductive layer.

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

Abstract: The present invention relates to a master cylinder arrangement (1) for a brake system (10), comprising a tandem master cylinder (2) including a master cylinder housing (20), a first master piston (23) movably arranged in the master cylinder housing (20), a second master piston (24) movably arranged in the master cylinder housing (20), a balancing piston (7) movably arranged in the second master piston (24), and an elastic pedal feel element (50). The invention further relates to a hydraulic system for a brake system as well as a brake system (10).

Abstract: A brake system comprises a reservoir; a brake pedal; a master cylinder including a first master chamber, a second master chamber, a first master piston, and a second master piston; a first hydraulic circuit including at least one first hydraulic wheel brake; a second hydraulic circuit including at least one second hydraulic wheel brake; and a hydraulic pressure supplier including an actuator for pressurizing the first hydraulic circuit and the second hydraulic circuit depending on an operation of the brake pedal in a normal operating mode. The master cylinder further comprises a locking chamber and an elastic pedal feel element arranged in the first master chamber to be in contact with the first master piston and the second master piston for generating a pedal force when the brake pedal is operated while the second master piston is locked in the normal operating mode.

Abstract: An electronic device is provided and includes a first voltage trace, a second voltage trace, a first region electrode, a second region electrode, and a voltage source module. The second voltage trace is electrically insulated from the first voltage trace, the first region electrode is electrically connected to the first voltage trace, and the second region electrode is electrically connected to the second voltage trace. The voltage source module provides a first driving voltage to the first voltage trace and provides a second driving voltage to the second voltage trace, in which the first driving voltage is different from the second driving voltage.