Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.

Abstract: Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Abstract: In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

Abstract: A waterproof structure includes a housing and a waterproof button. The housing has a first surface, a first side surface, and a second surface. The first side surface is recessed in the first surface to define a first opening, the first side surface is connected between the first surface and the second surface, and the second surface is exposed from the first opening. The waterproof button is disposed in the first opening and includes at least one first water blocking structure, and the first water blocking structure is pressed and deformed to abut against the first side surface.

Abstract: Methods are disclosed herein that improve contours of trenches formed when fabricating vias and conductive lines of a multi-layer interconnect (MLI) structure. An exemplary device that can result from such methods includes a via of an MLI structure and a conductive line of the MLI structure disposed over the via. A first dielectric liner layer is disposed along sidewalls of the via and sidewalls of the conductive line. A thickness of the first dielectric liner layer is substantially the same along the sidewalls of the via. A thickness of the first dielectric liner layer increases along the sidewalls of the conductive line, such that the first dielectric liner layer has a tiger-tooth shape at each bottom corner of the conductive line. A second dielectric liner layer is disposed along the first dielectric liner layer that is disposed along the sidewalls of the via.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.