Patents by Inventor Che-Cheng Chang

Che-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming interconnection structure
    Patent number: 11075112
    Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Semiconductor Device and Method
    Publication number: 20210217750
    Abstract: A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.
    Type: Application
    Filed: March 8, 2021
    Publication date: July 15, 2021
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • WATERPROOF STRUCTURE
    Publication number: 20210212230
    Abstract: A waterproof structure includes a housing and a waterproof button. The housing has a first surface, a first side surface, and a second surface. The first side surface is recessed in the first surface to define a first opening, the first side surface is connected between the first surface and the second surface, and the second surface is exposed from the first opening. The waterproof button is disposed in the first opening and includes at least one first water blocking structure, and the first water blocking structure is pressed and deformed to abut against the first side surface.
    Type: Application
    Filed: November 6, 2020
    Publication date: July 8, 2021
    Inventors: Hung-Wen HSU, Che-Cheng CHANG, Jian-Lun CHEN
  • FIXING STRUCTURE FOR ELECTRONIC DEVICE
    Publication number: 20210210833
    Abstract: A fixing structure for an electronic device includes a mounting body and a mounting bracket. The mounting body includes a side surface, a bottom surface, and at least one limiting member disposed on the bottom surface. The limiting member includes a fixed end and a pillar. The pillar extends downward from the fixed end and protrudes from the bottom surface. The mounting bracket includes a fixing plate and a release assembly. The fixing plate is disposed under the bottom surface of the mounting body, and the fixing plate and the pillar are buckled with each other. The release assembly is disposed on the fixing plate, and the release assembly abuts against the side surface of the mounting body.
    Type: Application
    Filed: November 6, 2020
    Publication date: July 8, 2021
    Inventors: Ming-Huei LAI, Che-Cheng CHANG, Jian-Lun CHEN
  • Semiconductor device and manufacturing method thereof
    Patent number: 11043593
    Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
  • Method of forming FinFET devices with embedded air gaps
    Patent number: 11043408
    Abstract: A dummy gate layer is formed over a substrate. A patterned mask is formed over the dummy gate layer. The patterned mask includes an opening. The opening is etched into the dummy gate layer. The patterned mask serves as a protective mask as the opening is etched. A lateral etching process is performed to portions of the dummy gate layer laterally exposed by the opening. The lateral etching process etches away the dummy gate layer without substantially affecting the patterned mask. After the lateral etching process is performed, a dielectric material is formed in the opening. An air gap is formed in the dielectric material. After the air gap is formed, the patterned mask and portions of the dielectric material formed over the patterned mask are removed. The dummy gate layer is replaced with a metal-containing gate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Semiconductor structure and manufacturing method thereof
    Patent number: 11018019
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Fin field effect transistor
    Patent number: 11018261
    Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Semiconductor Device and Method
    Publication number: 20210143276
    Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 13, 2021
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric
    Patent number: 11004846
    Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Semiconductor structure and manufacturing method thereof
    Patent number: 11004795
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Method and Structure for FinFET Isolation
    Publication number: 20210134680
    Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Che-Cheng Chang, Chih-Han Lin, Jr-Jung Lin
  • Method of forming interconnection structure with anti-adhesion liner
    Patent number: 10998226
    Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Integrated circuit device fins
    Patent number: 10998428
    Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Chiang Hung, Wei-Hao Huang
  • Semiconductor device and manufacturing method thereof
    Patent number: 10998312
    Abstract: A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Source/drain regions in fin field effect transistors (finFETs) and methods of forming same
    Patent number: 10998313
    Abstract: An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • FINFET ISOLATION STRUCTURE
    Publication number: 20210119035
    Abstract: A device includes a semiconductive substrate, a semiconductive fin, a stop layer, a fin isolation structure, and a spacer. The semiconductive fin is over the substrate. The stop layer is between the semiconductive substrate and the semiconductive fin. The fin isolation structure is in contact with the semiconductor fin and over the stop layer. A topmost surface of the fin isolation structure is higher than a topmost surface of the semiconductive fin. The spacer at least partially extends along a sidewall of the fin isolation structure.
    Type: Application
    Filed: December 6, 2020
    Publication date: April 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng CHANG, Chih-Han LIN, Horng-Huei TSENG
  • Interconnection structure with anti-adhesion layer
    Patent number: 10985055
    Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure, a conductive structure and an anti-adhesion layer. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The via opening has a sidewall. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. The anti-adhesion layer is present between the sidewall of the via opening of the dielectric structure and the conductive structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • SEMICONDUCTOR DEVICE
    Publication number: 20210111266
    Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin CHEN, Che-Cheng CHANG, Chih-Han LIN
  • Via Structure and Methods Thereof
    Publication number: 20210111119
    Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.
    Type: Application
    Filed: November 30, 2020
    Publication date: April 15, 2021
    Inventors: Che-Cheng Chang, Chih-Han Lin