Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

Abstract: Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. In response to an uncorrectable marking command issued by a host, the controller operates the cyclic redundancy check engine to encode a data pattern with a biased encoding seed to generate biased cyclic redundancy check code. The controller programs the data pattern and the biased cyclic redundancy check code to the non-volatile memory. The data pattern, therefore, will not pass CRC. The uncorrectable marking command works.

Abstract: A method for performing read acceleration, an associated data storage device and controller thereof are provided, where the method is applicable to the data storage device and the controller. The method includes: receiving a write command from a host device, and performing programming on a non-volatile (NV) memory element within a plurality of NV memory elements according to the write command; recording operation command-related information corresponding to the write command; when a read command having high priority exists in a queue corresponding to the NV memory element, suspending performing programming on the NV memory element; executing the read command; and after executing the read command, continuing performing programming on the NV memory element at least according to the operation command-related information.

Abstract: The invention introduces a method for multi-namespace data access, performed by a controller, at least including: obtaining a host write command from a host, which includes user data and metadata associated with one Logical Block Address (LBA) or more; and programming the user data and the metadata into a user-data part and a metadata part of a segment of a Logical Unit Number (LUN), respectively, wherein a length of the metadata part is the maximum metadata length of a plurality of LBA formats that the controller supports.

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Abstract: The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.

Abstract: A package structure for a semiconductor device includes a first conductive layer, a second conductive layer, a first die, a second die, a plurality of first blind via pillars and a conductive structure. The first conductive layer has a first surface and a second surface. The first die and the second die respectively have an active surface and a back surface, which are disposed opposite to each other. There is a plurality of metal pads disposed on the active surface. The first die is attached to the first surface of the first conductive layer with its back surface, and the second die is attached to the second surface of the first conductive layer with its back surface. The first and second conductive layers, the first and second dies, the first blind hole pillars and conductive structure are covered by a dielectric material.

Abstract: High-efficiency control technology for non-volatile memory is shown. A controller allocates spare blocks of a non-volatile memory to provide a first active block and writes data issued by a host to the first active block. When the number of spare blocks is less than a threshold number and valid data of a first source block is less than a critical data amount, the controller uses the first active block as a data transfer destination for the valid data from the first source block.

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Abstract: A manufacturing method for a semiconductor package structure, which includes the steps of providing a circuit build-up substrate, which has a first surface that exposes multiple flip-chip bonding pads and multiple first bonding pads located around the flip-chip bonding pads; forming a conductive substrate embedded with a chip and multiple conductive pillars on the first surface of the circuit build-up substrate, in which the first surface of the chip is disposed corresponding to the flip-chip bonding pads and the second end of the conductive pillars is disposed corresponding to the first bonding pads; a second surface of the chip and a first end of each conductive pillars are exposed from an upper surface of the conductive substrates; and arranging a memory module on the conductive substrate, corresponding to the first end of the conductive pillars, wherein the memory module and the chip do not overlap in an orthographic projection direction.

Abstract: A memory device includes a non-volatile (NV) memory including a plurality of NV memory elements. A method for performing programming management of the NV memory includes: setting a programming sequence of the NV memory elements; determining a selection interval between each of the NV memory elements according to the programming sequence and a serial number of each of the NV memory elements; for a target NV memory element of the plurality of NV memory elements in the programming sequence, determining a serial number of an immediately previous NV memory element in the programming sequence according to the selection interval and a serial number of the target NV memory element; determining whether the immediately previous NV memory element is in a busy state; and only when the immediately previous NV memory element is not in the busy state, programming the target NV memory element.

Abstract: A boost class-D amplifier includes a PWM modulator, a boost level controller coupled to the PWM modulator, a pre-driver coupled to the PWM modulator and the boost level controller, a system voltage source, an inductor coupled to the system voltage source, a first switch, a second switch, a third switch, a fourth switch, a first diode coupled between the third switch and a voltage ground, a second diode coupled between the fourth switch and the voltage ground, and a capacitor coupled between the first switch and the fourth switch. The PWM modulator is for receiving an input signal and generating a first modulated signal accordingly. The boost level controller is for receiving the first modulated signal and generating a second modulated signal accordingly. The pre-driver is for receiving the first modulated signal and the second modulated signal and generating control signals accordingly.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: A constant on-time controller (COT) includes: a voltage dividing circuit to generate a feedback voltage according to an output voltage of a buck regulator; a current ripple extracting circuit to sense a current from an inductor of a buck regulator, and generate an extracted ripple current having no DC component according to a sensed current; a one-shot on-timer to output a constant-on time control signal according to a regulator input voltage of the buck regulator and the output voltage; a comparing circuit to output a comparison result according to a reference voltage signal, the feedback voltage and the extracted ripple current; and a logic circuit to generate a control signal to the buck regulator according to the comparison result and the constant-on time control signal. The current ripple extracting circuit detects the DC component in the present cycle, and compares the detected DC component with the next cycle.

Abstract: This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

Abstract: A method for performing programming management, associated memory device and a controller thereof are provided. The memory device may include a non-volatile (NV) memory, and the NV memory may include a plurality of NV memory elements. The method may include: before programming a target NV memory element of the plurality of NV memory elements, checking whether another NV memory element of the plurality of NV memory elements is in a busy state or in a non-busy state; and when the other NV memory element enters the non-busy state, programming the target NV memory element.

Abstract: An adjustment structure of a hydraulic brake system is provided, which includes a main body, a piston and an adjusting device. The main body includes at least one fluid reservoir, an inner chamber and at least one fluid passage. The inner chamber includes a cylinder channel and an opening part, and the cylinder channel is communicated with the fluid reservoir by at least one fluid port. The piston is driven by the brake cable to be limitedly moved in the cylinder channel. The piston includes a cable hole for receiving the brake cable, and the piston has a normal operated position relative to the fluid port. The adjusting device is disposed in the opening part and is abutted against the piston. The adjusting device is operated to be moved relative to the brake cable such that the piston is adjusted to be returned to the normal operated position.

Abstract: A power control circuit includes an alternating current (AC) power source, a rectifier and a valley-fill circuit. The AC power source is configured to receive an AC voltage. The rectifier is configured to convert the AC voltage into a rectified voltage. The valley-fill circuit includes: an inductor, having a first terminal coupled to the rectifier, and a second terminal; a first resistor, having a first terminal coupled to the second terminal of the inductor, and a second terminal; a diode, having a cathode coupled to the second terminal of the inductor, and an anode; and a first capacitor, having a first terminal coupled to the second terminal of the first resistor and the anode of the diode, and a second terminal coupled to ground.